Device and procedure for measuring memory cell currents

• US 7,379,339 B2
• Filed: 11/16/2005
• Issued: 05/27/2008
• Est. Priority Date: 11/17/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Rogl, Stephan, Paparisto, Edvin
• Primary Examiner(s): Elms; Richard T.
• Assistant Examiner(s): LE, TOAN K
• Application Number:
  US11/274,483
• Publication Number:
  US 20060126388A1
• Time in Patent Office: 923 Days
• Field of Search: 365/185.21, 365/210, 365/201, 365/189.01, 365/198
• US Class Current: 365/185.21
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

The invention relates to a procedure and a device for measuring memory cell currents, in particular for non-volatile memory components, where the device has a current mirroring device for mirroring a current flowing through a memory cell when it is being read, and delivering an analog current signal generated during the mirroring, or an analog current signal derived from it, to an analog output pad of a memory component.

Claims

1. A device for measuring memory cell currents, the device comprising:

a current mirroring device for mirroring a current flowing through a memory cell when it is being read and delivering an analog current signal generated during mirroring, or an analog current signal derived from it, to an analog output pad of a memory component; and

an activation/deactivation device comprising a first circuit device connected between the current mirroring device and a memory cell read circuit.

2. The device according to claim 1, wherein the current mirroring device comprises a field-effect transistor.

3. The device according to claim 2, wherein a source or drain output of the transistor is connectable with the analog output pad of the memory component.

4. The device according to claim 2, wherein the memory cell read circuit comprises a field-effect transistor.

5. The device according to claim 4, wherein the memory cell read circuit comprises a further field-effect transistor.

6. The device according to claim 4, wherein a gate of the current mirroring device comprises a field-effect transistor is connectable with the gate of the memory cell read circuit transistor.

7. The device according to claim 6, wherein the gate of the memory cell read circuit transistor is coupled to a drain of the memory cell read circuit transistor.

8. The device according to claim 6, wherein a source of the memory cell read circuit transistor is coupled to a source of the current mirror transistor.

9. The device according to claim 1, wherein the activation/deactivation device deactivates the current mirroring device during a normal operation of the memory component, and activates the current mirroring device during a test operation of the memory component.

10. The device according to claim 9, wherein the activation/deactivation device comprises a second circuit device connected between the current mirroring device and the analog output pad.

11. The device according to claim 1, wherein the first circuit device comprises a transistor and/or a transmission gate.

12. The device according to claim 1, wherein the device for measuring memory cell currents is part of a sense amplifier device.

13. The device according to claim 1, wherein the analog current signal generated during mirroring is delivered to the analog output pad.

14. The device according to claim 1, wherein the analog current signal derived from the current signal generated during mirroring is delivered to the analog output pad.

15. A device for measuring memory cell currents, the device comprising:

a current mirroring device for mirroring a current flowing through a memory cell when it is being read and delivering an analog current signal derived from the current mirroring device to an output; and

an activation/deactivation device coupled between the current mirroring device and a memory cell read circuit.

16. The device according to claim 15, wherein the activation/deactivation device comprises a transmission gate.

17. The device according to claim 15, wherein the output comprises an analog bus.

18. The device according to claim 15, wherein the output comprises an analog output pad.

19. The device according to claim 15, further comprising an amplifier coupled to the output.

20. The device according to claim 15, wherein the output is coupled to a micro-controller.

21. A device for measuring memory cell currents, the device comprising a current mirroring device for mirroring a current flowing through a memory cell when it is being read, the current mirroring device coupled to an analog output pad of a memory component, wherein an analog current derived from or generated by the current mirroring device is delivered to the analog output pad while the memory component is in a test mode.

22. The device of claim 21, further comprising a memory cell read circuit coupled to the memory cell.

23. The device of claim 22, further comprising an activation/deactivation circuit coupled to the current mirroring device and coupled to the memory cell.

24. The device of claim 23, wherein the activation/deactivation circuit activates the current mirroring device during the test mode.

25. The device of claim 23, wherein the activation/deactivation circuit deactivates the current mirroring device during a normal operation mode.