Integrated passive devices

• US 7,382,056 B2
• Filed: 01/06/2005
• Issued: 06/03/2008
• Est. Priority Date: 04/29/2004
• Status: Expired due to Fees

• Current Assignee: Sychip Incorporated (Murata Manufacturing Co Limited)
• Original Assignee: Sychip Incorporated (Murata Manufacturing Co Limited)
• Inventors: Gao, Charley Chunlei, Sun, Kunquan, Degani, Yinon, Chiu, Anthony M., Sun, Liquo
• Primary Examiner(s): Baumeister; Bradley W.
• Assistant Examiner(s): Fulk; Steven J
• Application Number:
  US11/030,754
• Publication Number:
  US 20050253257A1
• Time in Patent Office: 1,244 Days
• Field of Search: 257/725, 257/724, 257/701, 257/777, 257/E23.005, 438/108, 438/109
• US Class Current: 257/777
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48237 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49822 Multilayer substrates multilayer metallisation on monolayer substrate H01L23/498
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 27/016 : Thin-film circuits
• CPC Class Codes: H01L 28/10 : Inductors
• CPC Class Codes: H01L 28/20 : Resistors
• CPC Class Codes: H01L 28/40 : Capacitors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19011 : including integrated passive components
• CPC Class Codes: H01L 2924/19015 : including thin film passive components
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/19103 : interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

The specification describes a multi-chip module (MCM) that contains an integrated passive device (IPD) as the carrier substrate (IPD MCM). Parasitic electrical interactions are controlled at one or both interfaces of the IPD either by eliminating metal from the interfaces, or by selective use of metal in parts of the MCM that are remote from the sensitive device components. The sensitive device components are primarily analog circuit components, especially RF inductor elements. In the IPD layout, the sensitive components are segregated from other components. This allows implementation of the selective metal approach. It also allows parasitic interactions on top of the IPD substrate to be reduced by selective placement of IC semiconductor chips and IC chip ground planes. In preferred embodiments of the IPD MCM of the invention, the IPD substrate is polysilicon, to further minimize RF interactions. The various methods of assembling the module may be adapted to keep the overall thickness within 1.0 mm.

Claims

1. An integrated passive device multichip module (MCM IPD) comprising:

a. a substrate,

b. an IPD attached to the substrate with an attachment layer, wherein at least part of the attachment layer is non-conducting,

and wherein the IPD comprises a first portion containing at least one inductor component and a second portion containing at least one digital component and wherein the part of the attachment layer underneath the first portion of the IPD is non-conducting and the part of the attachment layer underneath the digital components is conducting.

2. The IPD MCM of claim 1 wherein the entire attachment layer is non-conducting.

3. The IPD MCM of claim 2 wherein there is no metal between the IPD and the substrate.

4. The IPD MCM of claim 1 wherein the IPD MCM further includes at least one integrated circuit (IC) chip mounted on the top of the IPD.

5. The IPD MCM of claim 1 wherein the top of the IPD is selectively covered with a ground plane.

6. The IPD MCM of claim 5 wherein the ground plane is selectively placed only on the second portion of the IPD.

7. The IPD MCM of claim 1 wherein the non-conducting portion of the attachment layer is electrically insulating thermally conducting die attach material.

8. The IPD MCM of claim 7 wherein the non-conducting portion of the attachment layer is alumina filled epoxy.

9. The IPD MCM of claim 1 wherein the IPD comprises a polysilicon wafer substrate with at least one thin film passive device on the polysilicon wafer.

10. The IPD MCM of claim 9 wherein the polysilicon wafer substrate has a resistivity of more than 0.1 KOhm-cm.

11. An integrated passive device multichip module (MCM IPD) comprising:

a. a substrate,

b. an IPD attached to the substrate with an attachment layer, at least a portion of which is non-conducting, the IPD comprising a first portion containing mainly RF components and a second portion containing mainly non-RF components, the IPD having a first surface over the first portion and a second surface under the first portion,

c. an IC chip mounted on the second portion of the IPD, the MCM IPD characterized in that the first and second surfaces of the IPD are devoid of metal.

12. The IPD MCM of claim 11 wherein the IPD comprises a polysilicon wafer substrate with at least one thin film passive device on the polysilicon wafer.

13. The IPD MCM of claim 12 wherein the polysilicon wafer substrate has a resistivity of more than 0.1 KOhm-cm.

14. The IPD MCM of claim 11 further including a MEMS device.

15. The IPD MCM of claim 11 further including a protective body covering the IPD MCM.

16. The IPD MCM of claim 15 wherein the overall thickness of the IPD MCM measured including the thickness of the IPD, the thickness of the IC chip and the thickness of the protective body, is less than 1.2 mm.

17. The IPD MCM of claim 16 wherein the overall thickness of the IPD MCM measured including the thickness of the IPD, the thickness of the IC chip and the thickness of the protective body, is less than 1.0 mm or less.

18. The IPD MCM of claim 15 wherein the IC chip is attached to the IPD with wire bonds.

19. The IPD of claim 15 wherein the IPD is a technology transition interface between the IC chip and the PCB.

20. The IPD MCM of claim 19 wherein the IC chip is attached to the IPD with solder bumps having a first pitch, the IPD is attached to a PCB, and the PCB is attached to a system support substrate with solder bumps having a second pitch, wherein the first pitch is significantly smaller than the second pitch.