Semiconductor structures and memory device constructions

• US 7,391,070 B2
• Filed: 08/10/2005
• Issued: 06/24/2008
• Est. Priority Date: 05/26/2004
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Juengling, Werner
• Primary Examiner(s): Tran; Minhloan
• Assistant Examiner(s): LIU, BENJAMIN T
• Application Number:
  US11/201,824
• Publication Number:
  US 20060011947A1
• Time in Patent Office: 1,049 Days
• Field of Search: 257/296, 257/302, 257/306, 257905-908, 257/E27.088, 257/E27.091, 257/E27.096
• US Class Current: 257/296
• CPC Class Codes: H01L 29/78642 Vertical transistors
• CPC Class Codes: H10B 12/05 Making the transistor
• CPC Class Codes: H10B 12/315 with the capacitor higher than a bit line
• CPC Class Codes: Y10S 257/908 Dram configuration with transistors and capacitors of pairs of cells along a straight line between adjacent bit lines

Abstract

The invention includes a semiconductor structure having a gateline lattice surrounding vertical source/drain regions. In some aspects, the source/drain regions can be provided in pairs, with one of the source/drain regions of each pair extending to a digit line and the other extending to a memory storage device, such as a capacitor. The source/drain regions extending to the digit line can have the same composition as the source/drain regions extending to the memory storage devices, or can have different compositions from the source/drain regions extending to the memory storage devices. The invention also includes methods of forming semiconductor structures. In exemplary methods, a lattice comprising a first material is provided to surround repeating regions of a second material. At least some of the first material is then replaced with a gateline structure, and at least some of the second material is replaced with vertical source/drain regions.

Claims

1. A memory device construction, comprising:

a semiconductor substrate;

a gate material positioned over at least a portion of the substrate, the gate material defining a lattice having an array of openings therein;

a pair of elevationally-elongated source/drain regions on the substrate and extending through the openings in the lattice of gate material, such that the source/drain regions are at least partially surrounded by the gate material in at least two orthogonal dimensions, one of the source/drain regions being a first source/drain region and consisting essentially of conductively-doped epitaxial silicon, the other source/drain region being a second source/drain region and consisting essentially of conductively-doped silicon which is not epitaxial, the first and second source/drain regions being gatedly connected to one another through the gate material;

a memory storage device electrically connected to either the first source/drain region or the second source/drain region; and

a digit line electrically connected to whichever of the first and second source/drain regions is not electrically connected to the memory storage device.

2. The construction of claim 1 wherein the memory storage device is electrically connected to the first source/drain region.

3. The construction of claim 1 wherein the memory storage device is electrically connected to the second source/drain region.

4. The construction of claim 1 wherein the digit line and memory storage device are elevationally over the first and second source/drain regions.

5. The construction of claim 1 wherein the first and second source/drain regions have a first horizontally cross-sectional width and a second horizontally cross-sectional width respectively;

and wherein the first and second horizontally cross-sectional widths are about the same as one another.

6. The construction of claim 1 wherein the first and second source/drain regions have a first horizontally cross-sectional width and a second horizontally cross-sectional width respectively;

and wherein the first and second horizontally cross-sectional widths are not about the same as one another.

7. The construction of claim 6 wherein the second horizontally cross-sectional width is less than the first horizontally cross-sectional width.

8. The construction of claim 6 wherein the first horizontally cross-sectional width is less than the second horizontally cross-sectional width.

9. The construction of claim 6 wherein the memory storage device is a capacitor.

10. The construction of claim 6 wherein the memory storage device and gate material are together comprised by a DRAM cell.

11. A memory device construction, comprising:

a semiconductor substrate;

a gate material positioned over at least a portion of the substrate;

first and second elevationally-elongated source/drain pillars on the substrate and at least partially surrounded by the gate material;

a memory storage device electrically connected to said first source/drain pillar;

a digit line electrically connected to said second source/drain pillar; and

wherein;

the first source/drain pillar consists essentially of a first conductively-doped semiconductor material having an uppermost region doped to a first conductivity type and a remainder doped to a second conductivity type opposite the first conductivity type;

the second source/drain pillar consists essentially of a second conductively-doped semiconductor material having an uppermost region doped to the first conductivity type, and a remainder doped to the second conductivity type; and

the substrate comprises a channel segment extending between the first and second source/drain pillars and doped to the second conductivity type, the channel segment defining a longitudinal axis; and

the gate material extends along sidewalls of the first and second source/drain pillars that are substantially parallel to the longitudinal axis.

12. The construction of claim 11 wherein the first conductivity type is n-type and the second conductivity type is p-type.

13. The construction of claim 11 wherein the first conductivity type is p-type and the second conductivity type is n-type.

14. The construction of claim 11 wherein the digit line is elevationally over the second source/drain pillar.

15. The construction of claim 11 wherein one of the first and second conductively-doped semiconductor materials consists essentially of conductively-doped epitaxial semiconductor material and the other consists essentially of conductively doped semiconductor material which is not epitaxial.

16. The construction of claim 15 wherein the first conductively-doped semiconductor material consists essentially of the conductively-doped epitaxial semiconductor material.

17. The construction of claim 15 wherein the second conductively-doped semiconductor material consists essentially of the conductively-doped epitaxial semiconductor material.

18. The construction of claim 11 wherein the memory storage device and gateline are together comprised by a DRAM cell.

19. A memory device construction, comprising:

a semiconductor substrate;

a gateline over the substrate;

a pair of elevationally-elongated source/drain regions over the substrate and at least partially surrounded by the gateline, one of the source/drain regions being a first source/drain region and the other source/drain region being a second source/drain region;

a memory storage device electrically connected to said first source/drain region;

a digit line electrically connected to said second source/drain region; and

wherein;

the first source/drain region consists essentially of a first conductively-doped semiconductor material having an uppermost region doped to n+, and a remainder doped to n−

;

the second source/drain region consists essentially of a second conductively-doped semiconductor material having an uppermost region doped to n+, and a remainder doped to p; and

the substrate comprises;

a first conductively-doped diffusion region ohmically connected to the first source/drain region and doped to n−

;

a second conductively-doped diffusion region ohmically connected to the second source/drain region and doped to p−

; and

a segment extending from the first conductively-doped diffusion region to the second conductively-doped diffusion region and doped to p−

.

20. The construction of claim 19 wherein the first and second conductively-doped semiconductor materials consist essentially of epitaxial silicon.

21. The construction of claim 19 wherein one of the first and second conductively-doped semiconductor materials consists essentially of conductively-doped epitaxial silicon and the other comprises consists essentially of conductively-doped silicon which is not epitaxial.

22. The construction of claim 21 wherein the conductively-doped silicon which is not epitaxial is conductively-doped polycrystalline silicon.

23. The construction of claim 21 wherein the second conductively-doped semiconductor material consists essentially of the conductively-doped epitaxial silicon.

24. The construction of claim 21 wherein the memory storage device and gateline are together comprised by a DRAM unit cell.