CMOS image sensor with dark current reduction

• US 7,397,076 B2
• Filed: 10/22/2004
• Issued: 07/08/2008
• Est. Priority Date: 10/23/2003
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Jang, Hoon
• Primary Examiner(s): Huynh; Andy
• Assistant Examiner(s): HO, HOANG QUAN TRAN
• Application Number:
  US10/971,590
• Publication Number:
  US 20050087783A1
• Time in Patent Office: 1,355 Days
• Field of Search: None
• US Class Current: 257/292
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/14656 Overflow drain structures
• CPC Class Codes: H01L 27/14689 MOS based technologies

Abstract

Disclosed are a CMOS image sensor and a fabrication method thereof, which is adequate to reduce dark current. The CMOS image sensor comprises a device isolation region and an active region, which are formed on a semiconductor substrate; a photocharge generating portion formed on the active region for absorbing light externally and generating and accumulating charges; a transistor portion including at least one transistor for processing the charges accumulated in the photocharge generating portion; and a control terminal for preventing dark current from being introduced into the photocharge generating portion, and ejecting the dark current after temporally storing the dark current. The control terminal is operated to store the dark current for an integration time when a photodiode as the photocharge generating portion receives light, and eject the stored dark current by being grounded when the reset transistor is turned on.

Claims

1. A CMOS image sensor comprising:

a device isolation region and an active region in a semiconductor substrate;

a photocharge generating portion in the active region for absorbing external light and generating and accumulating charges;

a separating film between the device isolation region and the photocharge generating portion;

a transistor portion including at least one transistor for processing the charges accumulated in the photocharge generating portion; and

a control terminal in the active region having a maximum depth greater than that of the photocharge generating portion, at a boundary with the device isolation region and having the same conductive type as the photocharge generating portion for preventing dark current from being introduced from the device isolation region into the photocharge generating portion, and ejecting the dark current after temporally storing the dark current.

2. The CMOS image sensor of claim 1, wherein the transistor portion includes a reset transistor, a select transistor and an access transistor.

3. The CMOS image sensor of claim 2, wherein the control terminal stores the dark current for an integration time when light is received, and ejects the stored dark current by being grounded when the reset transistor is turned on.

4. The CMOS image sensor of claim 1, wherein the separating film separates the photocharge generating portion from the control terminal.

5. The CMOS image sensor of claim 1, wherein the photocharge generating portion comprises a photodiode.

6. The CMOS image sensor of claim 1, wherein the semiconductor substrate comprises a P-type semiconductor substrate.

7. The CMOS image sensor of claim 1, wherein the photocharge generating portion comprises an N+ implant.

8. The CMOS image sensor of claim 1, wherein the control terminal comprises an N+ implant.

9. The CMOS image sensor of claim 1, wherein the control terminal comprises a halo junction.

10. The CMOS image sensor of claim 1, wherein the control terminal has a voltage of about zero when the reset transistor is on.

11. The CMOS image sensor of claim 1, wherein the control terminal has a voltage corresponding to a depth of a potential well according to a characteristic of the photocharge generating portion.

12. The CMOS image sensor of claim 1, wherein the control terminal has a depth greater than the separating film.

13. The CMOS image sensor of claim 1, wherein the photocharge generating portion has a depth greater than the separating film.

14. The CMOS image sensor of claim 1, wherein the photocharge generating portion comprises impurities of a second conductivity type, and the separating film comprises impurities of a first conductivity type.

15. The CMOS image sensor of claim 1, wherein the control terminal comprises impurities of a second conductivity type, and the separating film comprises impurities of a first conductivity type.

16. The CMOS image sensor of claim 15, wherein the photocharge generating portion comprises impurities of a second conductivity type.

17. The CMOS image sensor of claim 15, wherein the semiconductor substrate comprises impurities of a first conductivity type.

18. The CMOS image sensor of claim 15, wherein the control terminal comprises an N implant, and the separating film comprises a P+ implant.