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Method for manufacturing resist pattern and method for manufacturing semiconductor device

  • US 7,405,033 B2
  • Filed: 01/14/2004
  • Issued: 07/29/2008
  • Est. Priority Date: 01/17/2003
  • Status: Expired due to Fees
First Claim
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1. A method of manufacturing a semiconductor device comprising:

  • discharging a first composition containing a first photosensitizer on a first conductive layer to form a plurality of first resist patterns under reduced pressure;

    exposing the plurality of first resist patterns by irradiation of light using a first photomask, the light having a photosensitive wavelength region of the first photosensitizer, wherein a first portion where the light is irradiated and a second portion where the light is not irradiated are formed in each of the plurality of first resist patterns;

    removing one of the first portion and the second portion by developing the plurality of first resist patterns to form a plurality of second resist patterns;

    etching the first conductive layer by using the plurality of second resist patterns as a mask to form a plurality of gate wirings and a plurality of gate electrodes over a substrate;

    removing the plurality of second resist patterns on the first conductive layer;

    forming an insulating film over the plurality of gate wirings and the plurality of gate electrodes;

    forming a plurality of semiconductor islands over the plurality of gate electrodes with said insulating film interposed therebeween;

    discharging a second composition containing a second photosensitizer on a second conductive layer to form a plurality of third resist patterns under reduced pressure;

    exposing the plurality of third resist patterns by irradiation of light using a second photomask, the light having a photosensitive wavelength region of the second photo sensitizer, wherein a third portion where the light is irradiated and a fourth portion where the light is not irradiated are formed in each of the plurality of third resist patterns;

    removing one of the third portion and the fourth portion by developing the plurality of third resist patterns to form a plurality of fourth resist patterns;

    etching the second conductive layer by using the plurality of fourth resist patterns as a mask to form a plurality of pixel electrodes arranged in a matrix form over the substrate;

    removing the plurality of fourth resist patterns on the second conductive layer;

    discharging a third composition containing a third photosensitizer on a third conductive layer to form a plurality of fifth resist patterns under reduced pressure;

    exposing the plurality of fifth resist patterns by irradiation of light using a third photomask, the light having a photosensitive wavelength region of the third photosensitizer, wherein a fifth portion where the light is irradiated and a sixth portion where the light is not irradiated are formed in each of the plurality of fifth resist patterns;

    removing one of the fifth portion and the sixth portion by developing the plurality of fifth resist patterns to form a plurality of sixth resist patterns;

    etching the third conductive layer by using the plurality of sixth resist patterns as a mask to form a plurality of source wirings wherein said plurality of source wirings extend across said plurality of gate wirings; and

    removing the plurality of sixth resist patterns on the third conductive layer.

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