Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor

• US 7,405,117 B2
• Filed: 05/15/2006
• Issued: 07/29/2008
• Est. Priority Date: 11/13/2003
• Status: Expired due to Term

• Current Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Original Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: You, Budong, Zuniga, Marco A.
• Primary Examiner(s): Nguyen; Tuan H
• Application Number:
  US11/435,079
• Publication Number:
  US 20060205168A1
• Time in Patent Office: 806 Days
• Field of Search: 438/133, 438/135, 438/136, 438/197, 438/275, 438/286, 438/301, 438/303, 438/305, 438/306
• US Class Current: 438/197
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823892 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/086 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/66681 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/66689 with a step of forming an insulating sidewall spacer forming insulating material on a substrate H01L21/02107
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A method of monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow, is disclosed.

Claims

1. A method of fabricating a transistor having a source region, a drain region and a gate region on a substrate, the method comprising:

implanting, into a surface of the substrate, a high voltage (HV) n-doped n-well with a first volume and a first surface area;

forming a gate oxide between a source region and a drain region of the transistor;

implanting, into the source region of the transistor, a p-doped p-body with a second volume and a second surface area after forming the gate oxide;

covering the gate oxide with a conductive material;

forming a source-side oxide spacer and a drain-side oxide spacer on sidewalls of the gate oxide;

implanting, into the source region of the transistor, a n-doped n+ region with a third volume and a third surface area and a p-doped p+ region with a fourth volume and a fourth surface area;

implanting, into the drain region of the transistor, a n-doped n+ region with a fifth volume and a fifth surface area; and

implanting, into the drain region of the transistor, a n-doped lightly doped drain that is shallower than the n-doped n+ region and having a portion which extends beneath the drain-side oxide spacer, the n-doped lightly doped drain having a sixth volume and a sixth surface area.

2. The method of claim 1, wherein implanting the p-doped p-body includes:

a first implant to limit a vertical depth of the p-doped p-body; and

a second implant separate from the first implant to control a lateral channel length of the transistor.

3. The method of claim 2, wherein the first implant is a high energy implant.

4. The method of claim 2, wherein the first implant is a large angle tilt implant.

5. The method of claim 2, wherein the first implant is deeper than the second implant.

6. The method of claim 2, wherein the first implant to limit the vertical depth of the p-doped p-body and the second implant to control the lateral channel length of the transistor both occur after formation of the gate oxide.

7. The method of claim 1, wherein the HV n-doped n-well and the n-doped lightly doped drain have a lower concentration of impurities than the n-doped n+ region and the p-doped p+ region of the source.

8. The method of claim 1, wherein the second surface area is located within the first surface area, and the third surface area and the fourth surface area are located within the second surface area.

9. The method of claim 1, wherein the n-doped lightly doped drain is self aligned to the gate region of the transistor and is implanted after forming the gate oxide of the transistor.

10. The method of claim 1, wherein the n-doped lightly doped drain is non-self aligned to the gate region of the transistor and is implanted prior to forming the gate oxide of the transistor.

11. The method of claim 1, wherein the n-doped lightly doped drain is implanted prior to implanting the n-doped n+ region and the p-doped p+ region of the source and the n-doped n+ region of the drain.

12. The method of claim 1, wherein the substrate is a n-type substrate.

13. The method of claim 12, further comprising depositing a silicon-on-insulator on the n-type substrate.

14. The method of claim 1, further comprising implanting LOCOS field oxide in the drain region adjacent to the gate oxide.

15. The method of claim 1, wherein the spacing of the p-doped p-body from the n-doped lightly doped drain is sized such that the n-doped lightly doped drain is spaced a distance (d) away from the gate of the transistor as measured along a surface of the transistor.

16. The method of claim 1, further comprising implanting, into the source region of the transistor a lightly-doped double diffusion region with a seventh volume having a seventh surface area.

17. The method of claim 1, further comprising:

forming a field oxide on the drain region of the transistor.

18. The method of claim 1, wherein the n-doped lightly doped drain is implanted with a spacing from the p-doped p-body.

19. The method of claim 1, wherein the n-doped n+ region in the drain region is self-aligned to the gate region of the transistor, and is implanted after formation of the gate oxide.

20. The method of claim 1, wherein the portion of the n-doped lightly doped drain further extends beneath a portion of the gate oxide.

21. A method of fabricating a semiconductor device comprising:

forming a first transistor including;

implanting, into a first surface of the substrate, a first impurity region with a first volume and a first surface area, the first impurity region being of a first type;

forming a first gate oxide between a source region and a drain region of the first transistor prior to implanting a second impurity region;

implanting, into the source region of the first transistor, the second impurity region with a second volume and a second surface area after forming the first gate oxide, the second impurity region being of an opposite second type relative to the first type;

covering the first gate oxide with a first conductive material;

forming a source-side oxide spacer and a drain-side oxide spacer on sidewalls of the first gate oxide;

implanting, into the source region of the transistor, a third impurity region with a third volume and a third surface area and a fourth impurity region with a fourth volume and a fourth surface area, the third impurity region being of the first type, the fourth impurity region being of the opposite second type;

implanting, into the drain region of the first transistor, a fifth impurity region with a fifth volume and a fifth surface area, the fifth impurity region being of the first type; and

implanting, into the drain region of the first transistor, a sixth impurity region with a sixth volume that is shallower than the fifth volume and a sixth surface area, the sixth impurity region being implanted with a spacing from the second impurity region and having a portion which extends beneath the drain-side oxide spacer, the sixth impurity region being of the first type.

22. The method of claim 21, further comprising:

forming a second transistor including;

implanting, into a second surface of the substrate, a seventh impurity region with a seventh volume and a seventh surface area, the seventh impurity region being of the first type;

forming a second gate oxide between a source region and a drain region of the second transistor;

covering the second gate oxide with a second conductive material;

implanting, into the source region of the second transistor, an eighth impurity region with an eighth volume and an eighth surface area, the eighth impurity region being of the opposite second type; and

implanting, into the drain region of the second transistor, a ninth impurity region with a ninth volume and a ninth surface area, the ninth impurity region being of the opposite second type.

23. The method of claim 22, further comprising:

forming a third transistor including;

implanting, into a third surface of the substrate, a tenth impurity region with a tenth volume and a tenth surface area, the tenth impurity region being of the second type;

forming a third gate oxide between a source region and a drain region of the third transistor;

covering the third gate oxide with a third conductive material;

implanting, into the source region of the third transistor, an eleventh impurity region with an eleventh volume and an eleventh surface area, the eleventh impurity region being of the first type; and

implanting, into the drain region of the third transistor, a twelfth impurity region with a twelfth volume and a twelfth surface area, the twelfth impurity region being of the first type.

24. The method of claim 23, wherein the first gate oxide, the second gate oxide and the third gate oxide are concurrently formed such that the first transistor, the second transistor and the third transistor have a similar threshold voltage and gate oxide thickness.

25. The method of claim 23, wherein the first gate oxide is formed at a different time than the second gate oxide and the third gate oxide.

26. The method of claim 23, wherein the first gate oxide, the second gate oxide and the third gate oxide have a same gate oxide thickness.

27. The method of claim 23, wherein the first gate oxide has a different gate oxide thickness than that of the second gate oxide or the third gate oxide.

28. The method of claim 23, wherein forming a first gate oxide includes forming the first gate oxide separately from and prior to formation of the second gate oxide and the third gate oxide.

29. The method of claim 23, wherein forming a sixth impurity region includes forming the sixth impurity region after formation of the second gate oxide and the third gate oxide.

30. The method of claim 23, wherein the first impurity region includes a high voltage n-type well lightly doped relative to a CMOS n-type well.

31. The method of claim 23, wherein the first impurity region includes a CMOS n-type well.

32. The method of claim 23, wherein the sixth impurity region includes a CMOS n-type well.

33. The method of claim 23, wherein the sixth impurity region includes a double doped drain.

34. The method of claim 23, wherein the sixth impurity region includes a lightly doped drain.

35. The method of claim 23, wherein implanting the second impurity region includes:

a first implant to limit a vertical depth of the second impurity region; and

a second implant separate from the first implant to control a lateral channel length of the transistor.

36. The method of claim 35, wherein the first implant and the second implant occur after formation of the second gate oxide and the third gate oxide.

37. The method of claim 21, further comprising implanting, into the source region of the first transistor, a thirteenth impurity region with a thirteenth volume and a thirteenth surface area, the thirteenth impurity region being of the first type.

38. The method of claim 37, wherein the thirteenth impurity region is adjacent to the third impurity region and extends beneath the first gate oxide.

39. The method of claim 21, wherein the first transistor is a p-type LDMOS transistor.

40. The method of claim 21, wherein the portion of the n-doped lightly doped drain further extends beneath a portion of the gate oxide.

41. A method of fabricating a transistor having a source region, a drain region and a gate region on a substrate, the method comprising:

implanting, into a surface of the substrate, a first impurity region with a first volume and a first surface area, the first impurity region being of a first type;

implanting, into the source region of the transistor, a second impurity region with a second volume and a second surface area, the second impurity region being of an opposite second type relative to the first type;

forming a gate oxide between the source region and the drain region of the transistor prior to implanting the second impurity region;

covering the gate oxide with a conductive material;

implanting, into the source region of the transistor, a third impurity region with a third volume and a third surface area and a fourth impurity region with a fourth volume and a fourth surface area, the third impurity region being of the first type, the fourth impurity region being of the opposite second type;

implanting, into the drain region of the transistor, a fifth impurity region with a fifth volume and a fifth surface area, the fifth impurity region being of the first type; and

implanting, into the drain region of the transistor, a plurality of sixth impurity regions each having a sixth volume and a sixth surface area, and is distanced apart from other sixth impurity regions along the first surface of the substrate, the sixth impurity region closest to the gate oxide being implanted with a spacing from the second impurity region, each sixth impurity region being of the first type.