Control component for controlling a semiconductor memory component in a semiconductor memory module

• US 7,405,993 B2
• Filed: 10/31/2006
• Issued: 07/29/2008
• Est. Priority Date: 09/18/2006
• Status: Active Grant

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Qimonda AG (Infineon Technologies AG)
• Inventors: Djordevic, Srdjan
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US11/589,984
• Publication Number:
  US 20080080292A1
• Time in Patent Office: 637 Days
• Field of Search: 365/230.03, 365/52, 365/230.02
• US Class Current: 365/230.03
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/1048 Data bus control circuits, e.g. precharging, presetting, equalising

Abstract

A semiconductor memory module includes a control component connected via various buses to semiconductor memory components on the top and bottom of a module board. Depending on the storage capacity and the rank configuration of the semiconductor memory module, address terminals are actuated via selection circuits either with address signals or control signals. According to an embodiment of the control component, control terminals are actuated with different control signals. The multiplexing of address and control signals allows the control component to control semiconductor memory components, in a semiconductor memory module, with different memory configurations without requiring an increased number of control terminals.

Claims

1. A control component for controlling a semiconductor memory component in a semiconductor memory module, comprising:

a control unit for generating control signals for controlling read and write access to the semiconductor memory component and for generating address signals for addressing memory cells in the semiconductor memory component for read and write access;

a plurality of address terminals for providing the address signals; and

a selection circuit for supplying one of the address terminals with a selected signal selected between one of the address signals and one of the control signals.

2. The control component as claimed in claim 1,

wherein the semiconductor memory component comprises a plurality of memory chips;

and

wherein the control unit generates a first of the control signal for selecting one of the memory chips for read and write access.

3. The control component as claimed in claim 2,

wherein each of the memory chips comprises an activatable terminating resistor that is activated for write access;

and

wherein the control unit generates a second control signal for activating the activatable terminating resistor of said one of the memory chips.

4. The control component as claimed claim 2, further comprising a second selection circuit, wherein the selection circuit supplies one of the address signals and a first of the control signals to a first of the address terminals, and the second selection circuit supplies one of the address signals and a second of the control signals to a second of the address terminals.

5. The control component as claimed in claim 4, further comprising a third selection circuit which supplies a first of the control signals and a second of the control signals to a first of the control terminals.

6. The control component as claimed in claim 5, further comprising a fourth selection circuit which supplies a second of the control terminals with one of a plurality of second control signals for selecting respective different ones of the memory chips for read and write access.

7. The control component as claimed in claim 1, wherein the control unit is supplied with a configuration signal and the selection circuit selects the selected signals based on the configuration signal.

8. The control component as claimed in claim 1, wherein the selection circuit comprises a multiplexer.

9. A semiconductor memory module, comprising:

a control component as claimed in claim 1;

a plurality of semiconductor memory components;

a module board on which the control component and the plurality of semiconductor memory components are arranged such that the plurality of semiconductor memory components are arranged on a left-hand and a right-hand side of the control component; and

a bus connecting each of the address terminals of the control component to the semiconductor memory components;

wherein the semiconductor memory components, arranged on the left-hand and right-hand sides of the control component, are connected to the control component via a bus connected to a first of the address terminals.

10. The semiconductor memory module as claimed in claim 9, further comprising:

a bus connecting each of the control terminals of the control component to the semiconductor memory components;

wherein the semiconductor memory components arranged on left-hand and right-hand sides of the control component, are connected to the control component via a bus connected to a second of the control terminals.

11. The semiconductor memory module as claimed in claim 9,

wherein a terminating resistor is arranged at a respective end of the buses.

12. The semiconductor memory module as claimed in claim 9, further comprising:

a memory circuit for storing a configuration state based on ranks arranged on the semiconductor memory module;

wherein the control circuit controls the selection circuit based on the configuration state stored in the memory circuit, such that one of the signals supplied to the selection circuit is selected.

13. The semiconductor memory module as claimed in claim 12,

wherein the memory circuit is an electrically programmable memory.

14. The semiconductor memory module as claimed in claim 9,

wherein the semiconductor memory components are operated in a 4Rx4 or 4Rx8 module configuration.

15. A method for operating a semiconductor memory module, comprising:

providing a semiconductor memory module as claimed in claim 9;

operating the semiconductor memory module in a first configuration when the semiconductor memory module includes a first number of ranks, and operating the semiconductor memory module in a second configuration when the semiconductor memory module includes a second number of ranks; and

generating one of the control signals controlling read and write access to the semiconductor memory component at one of the address terminals of the control component in the semiconductor memory module when the semiconductor memory module is operated in the first configuration, and generating one of;

the address signals, a floating potential and a reference potential at one of the address terminals when the semiconductor memory module is operated in the second configuration.

16. The method as claimed in claim 15, further comprising:

generating the first control signal, for selecting a memory chip in a semiconductor memory component for read or write access, at the first address terminal of the control component in the semiconductor memory module when the semiconductor memory module is operated in the first configuration, and generating one of;

a first address signal, the floating potential and the reference potential at the first address terminal when the semiconductor memory module is operated in the second configuration; and

generating the second control signal at the second address terminal when the semiconductor memory module is operated in the first configuration, and generating one of;

a second address signal, the floating potential and the reference potential at the second address terminal when the semiconductor memory module is operated in the second configuration.

17. The method as claimed in claim 15, comprising:

operating the semiconductor memory module in a first configuration in the event that the semiconductor memory module comprises a first number of ranks, and operating the semiconductor memory module in a second configuration in the event that the semiconductor memory module comprises a second number of ranks;

generating the first control signal at the first address terminal when the semiconductor memory module is operated in the first configuration, and generating one of;

a first address signal, a floating potential and a reference potential at the first address terminal in the event that the semiconductor memory module is operated in the second configuration; and

generating the second control signal at the first control terminal in the event that the semiconductor memory module is operated in the first configuration, and generating the first control signal at the first control terminal in the event that the semiconductor memory module is operated in the second configuration.

18. The method as claimed in claim 15, further comprising:

ascertaining the number of ranks on the semiconductor memory module via evaluating a memory state of the memory circuit, the memory state identifying the number of ranks on the semiconductor memory module.

19. The method as claimed in claim 15,

wherein the semiconductor memory module is operated in the first configuration in the event that the semiconductor memory module includes a number of four ranks;

wherein the semiconductor memory module is operated in the second configuration when the semiconductor memory module includes a number of two ranks.