Self-coplanarity bumping shape for flip-chip

• US 7,407,877 B2
• Filed: 06/03/2005
• Issued: 08/05/2008
• Est. Priority Date: 02/27/2001
• Status: Expired due to Term

• Current Assignee: Stats Chippac Pte. Lte.
• Original Assignee: Chippac Company Limited
• Inventors: Kweon, Young-Do, Pendse, Rajendra D., Kim, Kyung-Moon, Ahmad, Nazir
• Primary Examiner(s): Thai; Luan
• Application Number:
  US11/145,247
• Publication Number:
  US 20050221535A1
• Time in Patent Office: 1,159 Days
• Field of Search: 438/612, 438/613, 438/614, 438/108, 257/737, 257/738, 257/773, 257/780, 257/E23.021, 257/E23.069
• US Class Current: 438/612
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/1134 Stud bumping, i.e. using a wire-bonding apparatus
• CPC Class Codes: H01L 2224/11831 involving a chemical process, e.g. etching the bump connector
• CPC Class Codes: H01L 2224/1184 involving a mechanical process, e.g. planarising the bump connector
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/14 of a plurality of bump connectors
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/17 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A stud bump structure for electrical interconnection between a pair of members includes a base portion, and a stem portion. The base portion is affixed to a pad or trace in one of the pair of members to be interconnected (such as an integrated circuit chip), and the stem end is configured to contact a metal pad on the other member (such as a printed circuit board) to complete the interconnect. According to the invention, the stem end is truncated to form a transverse plane, and the stem is more compliant than the base. Also, a method for forming a stud bump on a contact surface, includes forming a bump base portion on the surface, drawing out a generally conical tail from a top of the base, and truncating the tail to form a stem portion having a planar transverse top surface and having a length from the top of the base portion to the top surface. In some embodiments the tail portion, at least, of the stud bump is formed using a wire bonding tool. Also, a method for forming an interconnect between a first member and a second member of an electronic package includes providing one of the members with the stud bumps of the invention and then bringing the corresponding bumps and pads together in a bonding process, the compliance of the stems portions of the bumps accommodating the variance from coplanarity of the pad surfaces.

Claims

1. A method of interconnecting a semiconductor device to a substrate, comprising:

providing a semiconductor device having a surface;

providing a substrate having a non-planar surface and a plurality of interconnect pads formed on the non-planar surface, each interconnect pad having a top surface which resides at a different level with respect to top surfaces of other interconnect pads due to the non-planar surface of the substrate, the interconnect pads of the substrate having a maximum range of noncoplanarity;

forming a plurality of interconnect bumps on the surface of the semiconductor device by,

(a) forming a base portion on the surface of the semiconductor device using a nickel or copper wirebonding process, the base portion having a flattened spheroidal shape, and

(b) forming a stem portion extending from the base portion using a solder material, the stem portion having a conical frustum shape and a first end adjacent to the base portion and a distal end with a transverse planar surface, the first end and the distal end of the stem portion being narrower than the base portion, the stem portion being more compliant than the base portion and the height of the stem portion being greater than the maximum range of noncoplanarity of the interconnect pads of the substrate;

apposing the semiconductor device and substrate such that the interconnect bumps align with the interconnect pads; and

bringing the distal end of the stem portion of each interconnect bump in contact with a corresponding interconnect pad on the non-planar surface by deforming the stem portions as necessary to accommodate the non-planar surface, the step of deforming the stem portions including using heat treatment to connect the stem portions of the interconnect bumps to the corresponding interconnect pads, the heat treatment using a temperature sufficient to deform the stem portions of the interconnect bumps while preventing deformation of the base portions.

2. The method of claim 1, wherein the stem portion is formed by chemical mechanical polishing.

3. The method of claim 1, wherein the first end of the stem portion is two times a diameter of the distal end.

4. The method of claim 1, wherein a height of the stem portion is at least 1.5 times a height of the base portion.

5. A method of interconnecting a semiconductor device to a substrate, comprising:

providing a semiconductor device having a surface;

forming a plurality of interconnect bumps on the surface of the semiconductor device by,

(a) forming a base portion on the surface of the semiconductor device, the base portion having a flattened spheroidal shape, and

(b) forming a stem portion extending from the base portion, the stem portion having a conical frustum shape and a first end adjacent to the base portion and a distal end, the stem portion being more compliant than the base portion;

providing a substrate having a non-planar surface and a plurality of interconnect pads formed on the non-planar surface; and

bringing the distal end of the stem portion of each interconnect bump in contact with a corresponding interconnect pad on the non-planar surface by deforming the stem portions as necessary to accommodate the non-planar surface, the step of deforming the stem portions including using heat treatment to connect the stem portions of the interconnect bumps to the corresponding interconnect pads, the heat treatment using a temperature sufficient to deform the stem portions of the interconnect bumps while preventing deformation of the base portions.

6. The method of claim 5, wherein each interconnect pad has a top surface which resides at a different level with respect to top surfaces of other interconnect pads due to the non-planar surface of the substrate.

7. The method of claim 5, wherein the stem portion is formed by chemical mechanical polishing.

8. The method of claim 5, wherein the base portion is made with a first material and the stem portion is made with a second material which is more compliant than the first material.

9. The method of claim 8, wherein the first material includes nickel or copper.

10. The method of claim 8, wherein the second material includes gold.

11. The method of claim 5, wherein the first end of the stem portion is two times a diameter of the distal end.

12. The method of claim 5, wherein a height of the stem portion is at least 1.5 times a height of the base portion.

13. A method of interconnecting a semiconductor device to a substrate, comprising:

providing a semiconductor device having a surface;

forming a plurality of interconnect bumps on the surface of the semiconductor device by,

(a) forming a base portion on the surface of the semiconductor device, and

(b) forming a stem portion extending from the base portion;

providing a substrate having a non-planar surface and a plurality of interconnect pads formed on the non-planar surface; and

bringing the stem portion of each interconnect bump in contact with a corresponding interconnect pad on the non-planar surface by deforming the stem portions as necessary to accommodate the non-planar surface, the step of deforming the stem portions including using heat treatment to connect the stem portions of the interconnect bumps to the corresponding interconnect pads, the heat treatment using a temperature sufficient to deform the stem portions of the interconnect bumps while preventing deformation of the base portions.

14. The method of claim 13, further including apposing the semiconductor device and substrate such that the interconnect bumps align with the interconnect pads.

15. The method of claim 13, wherein the base portion is made with a first material and the stem portion is made with a second material which is more compliant than the first material.

16. The method of claim 15, wherein the first material includes nickel or copper.

17. The method of claim 15, wherein the second material includes gold.

18. The method of claim 13, wherein the stem portion has a first end adjacent to the base portion and a distal end with a transverse planar surface.

19. The method of claim 18, wherein the first end of the stem portion is two times a diameter of the distal end.

20. The method of claim 18, wherein a height of the stem portion is at least 1.5 times a height of the base portion.