Apparatus and method for switchable conditional execution in a VLIW processor

• US 7,412,591 B2
• Filed: 06/18/2005
• Issued: 08/12/2008
• Est. Priority Date: 06/18/2005
• Status: Active Grant

• Current Assignee: Industrial Technology Research Institute
• Original Assignee: Industrial Technology Research Institute
• Inventors: Wang, Chi-Lung, Ma, Yung-Cheng, Wang, Tengh-Yih, Kuo, Hsien-Feng
• Primary Examiner(s): Treat; William M.
• Application Number:
  US11/155,120
• Publication Number:
  US 20060288195A1
• Time in Patent Office: 1,151 Days
• Field of Search: 712/24, 712/229
• US Class Current: 712/229
• CPC Class Codes: G06F 9/30072 to perform conditional operations, e.g. using predicates or guards
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3858 Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/38585 with result invalidation, e.g. nullification
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

An apparatus for switchable conditional execution in a VLIW processor is provided, comprising one or more decoders, one or more ALU with control units, and a register file. The decoder loads and decodes instructions from a fetch unit for decoding and sending the decoded instructions to the ALU with control units for execution. The register file stores and forwards the results on result buses to the decoders. The execution of a VLIW instruction includes a fetch stage, a decode stage, plural execution stages and a write-back stage. The invention has the features of approximate ASIC timing by conditional write-back with the compiler support for the conditional write-back, condition resolved just before write-back, software selective conditional issue and conditional write-back modes, and without hardware interlock/dependence checking for the VLIW processor.

Claims

1. An apparatus for switchable conditional execution (CE) in a very long instruction word (VLIW) processor, said apparatus comprising:

one or more instruction decoders being involved in a decode stage for loading and decoding instructions from a fetch unit, said one or more instruction decoders decoding conditional instructions for conditional execution in an energy-saving mode or a high-performance mode;

one or more arithmetic logic units (ALU) with control units, for executing the decoded instructions from said one or more instruction decoders; and

a register file including a plurality of registers for storing and forwarding the executed results of said ALU with control units to said one or more instruction decoders to support said conditional execution;

wherein said apparatus has a special instruction for switching said apparatus between said energy-saving mode and said high-performance mode for scheduling and executing conditional instructions in an in-order-scheduling fashion in said energy-saving mode and in an out-of-order-scheduling fashion in said high-performance mode.

2. The apparatus for switchable conditional execution as claimed in claim 1, wherein said processor has an instruction format comprising a CE field for indicating whether an instruction is a conditional instruction, and a source of condition of the conditional instruction.

3. The apparatus for switchable conditional execution as claimed in claim 2, wherein said source of said condition of the conditional instruction is the least significant bit of a register in said register file.

4. The apparatus for switchable conditional execution as claimed in claim 3, wherein the least significant bits of said registers of said register file are used as conditional bits that are broadcasted to other parts of said processor.

5. The apparatus for switchable conditional execution as claimed in claim 4, wherein said one or more instruction decoders propagate said CE field to said ALU with control units for execution when executing in said high-performance mode.

6. The apparatus for switchable conditional execution as claimed in claim 5, wherein each of said ALU with control units further comprises a functional unit and a recording unit, said functional unit determines whether to execute opcode of an instruction according to the conditional bits broadcasted by said register file, and said recording unit records the CE field propagated by said one or more instruction decoders.

7. The apparatus for switchable conditional execution as claimed in claim 4, wherein said one or more instruction decoders block said CE field and use said conditional bits broadcasted by said register file to determine whether opcode of an instruction should be set as an NOP to save energy when executing in said energy-saving mode.

8. The apparatus for switchable conditional execution as claimed in claim 1, wherein a conditional issue mode is used to execute the conditional instructions when executing in said energy-saving mode, while a conditional write-back mode is used to execute the conditional instructions when executing in said high-performance mode.

9. The apparatus for switchable conditional execution as claimed in claim 8, wherein said conditional issue mode resolves conditions for conditional instructions at said decode stage, while said conditional write-back mode resolves conditions for conditional instructions at a last execution stage.

10. The apparatus for switchable conditional execution as claimed in claim 1, wherein for each execution stage, a corresponding output enable line is generated by a corresponding ALU with control unit for indicating a different execution stage when executing in said high-performance mode.

11. The apparatus for switchable conditional execution as claimed in claim 3, wherein said register file further includes a forwarding circuit to broadcast the least significant bits to other parts of said processor.

12. The apparatus for switchable conditional execution as claimed in claim 1, wherein said apparatus is a digital signal processor.

13. A switchable conditional execution method performed in a very long instruction word (VLIW) processor, said method comprising the steps of:

(a) arranging an instruction format for the VLIW processor to switch between two conditional modes including a conditional issue mode and a conditional write-back mode;

(b) decoding conditional instructions using said instruction format for conditional execution in said conditional issue mode or said conditional write-back mode;

(c) dividing the execution of a VLIW instruction into a fetch stage, a decode stage, a plurality of execution stages, and a write-back stage; and

(d) resolving condition of a conditional instruction in said conditional issue mode at said decode stage, while resolving condition of a conditional instruction in said conditional write-back mode at a last execution stage.

14. The switchable conditional execution method as claimed in claim 13, wherein said method uses a special instruction for switching said processor between an energy-saving mode and a high-performance mode, and said conditional issue mode is used to execute the conditional instructions in an energy-saving mode, while said conditional write-back mode is used to execute the conditional instructions in a high-performance mode.

15. The switchable conditional execution method as claimed in claim 13, wherein conditional instructions are scheduled and executed in an in-order-scheduling fashion in said conditional issue mode, and in an out-of-order-scheduling fashion in said conditional write-back mode.