Semiconductor integrated circuit and semiconductor integrated circuit manufacturing method

• US 7,412,679 B2
• Filed: 08/19/2005
• Issued: 08/12/2008
• Est. Priority Date: 08/20/2004
• Status: Expired due to Fees

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Shimura, Hidekichi
• Primary Examiner(s): Kik; Phallaka
• Application Number:
  US11/206,863
• Publication Number:
  US 20060041774A1
• Time in Patent Office: 1,089 Days
• Field of Search: 716/9, 716/10, 716/13, 716/14, 326/63, 326/80, 326/101
• US Class Current: 716/120
• CPC Class Codes: H03K 19/0008 Arrangements for reducing power consumption

Abstract

A low-power-consumption type semiconductor integrated circuit incorporating a variety of functions and a semiconductor integrated circuit manufacturing method are provided. As an example of a semiconductor integrated circuit, a system LSI 1 has first circuit blocks 41 through 48 that do not include a critical path, second circuit blocks 51 through 54 that include a critical path, first power supply wiring 25 that supplies a first power supply to first circuit blocks 41 through 48, and second power supply wiring 26 that supplies a second power supply of higher voltage than the first power supply to second circuit blocks 51 through 54, with second circuit blocks 51 through 54 being connected to second power supply wiring 26 by means of wiring areas 61 through 64 respectively, and being supplied with the second power supply.

Claims

1. A semiconductor integrated circuit, comprising:

a first circuit block that does not include a critical path; and

a second circuit block that includes the critical path,

wherein a power supply voltage value supplied to the second circuit block for an operation is higher than a power supply voltage value supplied to the first circuit block for the operation;

wherein the second circuit block comprises a first flip-flop, a level shifter, a combination circuit and a second flip-flop, which are connected in series; and

wherein a threshold voltage of the combination circuit of the second circuit block is lower than threshold voltages of combination circuits other than the combination circuit of the second circuit block, and, in response to a standby request for the second circuit block, a supply of a power supply voltage supplied to the combination circuit of the second circuit block is cut off.

2. The semiconductor integrated circuit according to claim 1,

wherein the second circuit block comprises a plurality of circuit blocks with different power supply voltage values and different threshold voltages of combination circuits.

3. The semiconductor integrated circuit according to claim 1,

wherein, when the second circuit block is set to a standby state, a system clock supplied to the first flip-flop and the second flip-flop is stopped, and the supply of the power supply voltage supplied to the combination circuit of the second circuit block is cut off;

and

wherein, when the second circuit block is restored from the standby state, a power supply voltage is supplied to the combination circuit of the second circuit block, and then the system clock is supplied to the first flip-flop and the second flip-flop.