Method and related processing circuits for reducing memory accessing while performing de/compressing of multimedia files

• US 7,415,161 B2
• Filed: 03/25/2004
• Issued: 08/19/2008
• Est. Priority Date: 03/25/2004
• Status: Expired due to Fees

• Current Assignee: Novatek Microelectronics Corporation (Novatek Microelectronics Corp Limited)
• Original Assignee: Faraday Technology Corp.
• Inventors: Lee, Heng-Kuan
• Primary Examiner(s): Ahmed; Samir A
• Assistant Examiner(s): VANCHY JR, MICHAEL J
• Application Number:
  US10/708,786
• Publication Number:
  US 20050213829A1
• Time in Patent Office: 1,608 Days
• Field of Search: 382/239
• US Class Current: 382/239
• CPC Class Codes: H04N 19/426 using memory downsizing methods

Abstract

Method and apparatus for reducing memory access while de/compressing multimedia files, videos, or image files. An image is divided into blocks, and a frequency data matrix corresponding to a frequency transformed and quantized block is stored in a memory for later de/compression. The method includes registering a bit plane containing a plurality of bits in a register module, wherein each bit represents whether a corresponding element of the data matrix equals zero. While accessing the memory for the data matrix, if a bit of the bit plane shows that its corresponding element of the data array is zero, the element is not accessed from the memory. In checking bits corresponding to elements not yet accessed; if these bits show that elements not accessed are all zero, accessing for the data array can be terminated without accessing them. Thus, memory access can be reduced to occupy less bandwidth of the memory.

Claims

1. A data coding/decoding method comprising:

reading a frequency-domain matrix, the frequency-domain matrix comprising a plurality of frequency-domain elements;

providing a reference matrix comprising a plurality of reference elements each corresponding to a frequency-domain element, each reference element representing whether its corresponding frequency-domain element fits a default or not; and

taking a transformation step for generating an output matrix based on the frequency-domain matrix, the transformation step comprising;

taking a transformation checking step for checking if the reference matrix fits a default matrix;

if the reference matrix does not fit the default matrix, a corresponding output matrix is generated by proceeding to a transformation operation for the frequency-domain matrix; and

if the reference matrix fits the default matrix, the frequency-domain matrix is prevented from undergoing the transformation operation and the output matrix is a constant matrix.

2. The data coding/decoding method of claim 1 wherein at least one frequency-domain element is a direct current frequency-domain element and other frequency elements are alternating current frequency-domain elements among the plurality of frequency-domain elements;

wherein when the reference matrix fits the default matrix, each reference element corresponding to each alternating current frequency-domain element in the reference matrix represents that the alternating current frequency-domain element fits the default.

3. The data coding/decoding method of claim 2 further comprising:

when the reference matrix fits the default matrix, a constant operation step is performed for generating the constant matrix by working out a constant value based on the direct current frequency-domain element so that a plurality of elements of the constant matrix equal the constant value.

4. The data coding/decoding method of claim 1 wherein the default is null.

5. The data coding/decoding method of claim 1 wherein the transformation operation is an inverse discrete cosine transformation.

6. A processing circuit for data coding/decoding comprising:

a memory capable of storing a frequency-domain matrix, the frequency-domain matrix comprising a plurality of data elements;

a register module for storing a reference matrix wherein the reference matrix comprises a plurality of reference elements each corresponding to a frequency-domain element, each reference element for representing whether its corresponding frequency-domain element fits a default or not; and

a transformation module for providing a corresponding output matrix based on the frequency-domain matrix, the transformation module comprising;

a transformation operation module; and

a transformation checking module for checking if the reference matrix fits a default matrix;

wherein if the reference matrix does not fit the default matrix, the transformation checking module triggers the transformation operation module to proceed to a transformation operation for generating a corresponding output matrix, and if the reference matrix fits the default matrix, the transformation checking module is prevented from triggering the transformation operation module to proceed to the transformation operation for generating a corresponding output matrix and the output matrix is a constant matrix.

7. A processing circuit for data coding/decoding of claim 6 wherein at least one frequency-domain element is a direct current frequency-domain element and other frequency elements are alternating current frequency-domain elements among the plurality of frequency-domain elements;

wherein when the reference matrix fits the default matrix, each reference element corresponding to each alternating current frequency-domain element in the reference matrix represents that the alternating current frequency-domain element fits the default.

8. The processing circuit for data coding/decoding of claim 7 further comprising:

a constant operation module;

wherein when the reference matrix fits the default matrix, the transformation checking module triggers the constant operation module to generate a constant value and the constant matrix based on the direct current frequency-domain element so that a plurality of elements of the constant matrix equal the constant value.

9. The processing circuit for data coding/decoding of claim 6 wherein the default is null.

10. The processing circuit for data coding/decoding of claim 6 wherein the transformation operation module is capable of performing an inverse discrete cosine transformation.