Allocation of combined or separate data and control planes

• US 7,424,698 B2
• Filed: 02/27/2004
• Issued: 09/09/2008
• Est. Priority Date: 02/27/2004
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Honary, Hooman, Chen, Inching, Tsui, Ernest T.
• Primary Examiner(s): Siek; Vuthe
• Assistant Examiner(s): Dimyan; Magid Y
• Application Number:
  US10/789,187
• Publication Number:
  US 20050193357A1
• Time in Patent Office: 1,656 Days
• Field of Search: 716/16, 716/17
• US Class Current: 716/103
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A dual mesh interconnect network in a heterogeneous configurable circuit may be allocated between data communication and control communication.

Claims

1. A method comprising:

translating a design description into a configuration for a plurality of heterogeneous processing elements in a heterogeneous reconfigurable device coupled to routers interconnected by a plurality of mesh interconnect networks, the plurality of mesh interconnect networks being allocatable to either data or control or a combination thereof; and

allocating the plurality of mesh interconnect networks between data and control, wherein allocating comprises determining latency constraints so that said latency constraints are met with a shared data and control mesh network.

2. The method of claim 1 wherein the plurality of mesh interconnect networks includes a first plane and a second plane, and allocating comprises dedicating the first plane to control and dedicating the second plane to data.

3. The method of claim 1 wherein the plurality of mesh interconnect networks includes a first plane and a second plane, and allocating comprises allocating the first plane to be shared between data and control.

4. The method of claim 1 wherein the plurality of mesh interconnect networks includes a first plane and a second plane, and allocating comprises allocating both the first plane and the second plane to be shared between data and control.

5. The method of claim 1 wherein the plurality of heterogeneous processing elements are configurable to communicate over the plurality of mesh interconnect networks using packets of information.

6. A method comprising:

translating a design description into a configuration for a plurality of heterogeneous processing elements in a heterogeneous reconfigurable device coupled to routers interconnected by a plurality of mesh interconnect networks, the plurality of mesh interconnect networks being allocatable to either data or control or a combination thereof;

allocating the plurality of mesh interconnect networks between data and control, wherein translating and allocating results in a protocol file;

storing the protocol file in a memory; and

translating a second design description and performing a second allocation, resulting in a second protocol file, and storing the second protocol file in the memory.

7. The method of claim 6 wherein the plurality of mesh interconnect networks includes a first plane and a second plane, and allocating comprises dedicating the first plane to control and dedicating the second plane to data.

8. The method of claim 6 wherein the plurality of mesh interconnect networks includes a first plane and a second plane, and allocating comprises allocating the first plane to be shared between data and control.

9. The method of claim 6 wherein the plurality of mesh interconnect networks includes a first plane and a second plane, and allocating comprises allocating both the first plane and the second plane to be shared between data and control.

10. The method of claim 6 wherein the plurality of heterogeneous processing elements are configurable to communicate over the plurality of mesh interconnect networks using packets of information.

11. An apparatus including a computer storage device to hold machine-accessible instructions that when accessed result in a machine performing:

translating a design description into a configuration for a plurality of heterogeneous processing elements in a heterogeneous reconfigurable device coupled to routers interconnected by a plurality of mesh interconnect networks, the plurality of mesh interconnect networks being allocatable to either data or control or a combination thereof; and

allocating the plurality of mesh interconnect networks between data and control, wherein allocating comprises determining whether latency constraints so that said latency constraints are met with a shared data and control mesh network.

12. The apparatus of claim 11 wherein the plurality of mesh interconnect networks includes a first plane and a second plane, and allocating comprises dedicating the first plane to control and dedicating the second plane to data.

13. The apparatus of claim 11 wherein the plurality of mesh interconnect networks includes a first plane and a second plane, and allocating comprises allocating the first plane to be shared between data and control.

14. The apparatus of claim 11 wherein the plurality of mesh interconnect networks includes a first plane and a second plane, and allocating comprises allocating both the first plane and the second plane to be shared between data and control.

15. The apparatus of claim 11 wherein the plurality of heterogeneous processing elements are configurable to communicate over the plurality of mesh interconnect networks using packets of information.

16. An apparatus including a computer storage device to hold machine-accessible instructions that when accessed result in a machine performing:

translating a design description into a configuration for a plurality of heterogeneous processing elements in a heterogeneous reconfigurable device coupled to routers interconnected by a plurality of mesh interconnect networks, the plurality of mesh interconnect networks being allocatable to either data or control or a combination thereof;

allocating the plurality of mesh interconnect networks between data and control, wherein translating and allocating results in a protocol file;

storing the protocol file in a memory; and

translating a second design description and performing a second allocation, resulting in a second protocol file, and storing the second protocol file in the memory.

17. The apparatus of claim 16 wherein the plurality of mesh interconnect networks includes a first plane and a second plane, and allocating comprises dedicating the first plane to control and dedicating the second plane to data.

18. The apparatus of claim 16 wherein the plurality of mesh interconnect networks includes a first plane and a second plane, and allocating comprises allocating the first plane to be shared between data and control.

19. The apparatus of claim 16 wherein the plurality of mesh interconnect networks includes a first plane and a second plane, and allocating comprises allocating both the first plane and the second plane to be shared between data and control.

20. The apparatus of claim 16 wherein the plurality of heterogeneous processing elements are configurable to communicate over the plurality of mesh interconnect networks using packets of information.