Efficient and flexible GPS receiver baseband architecture
First Claim
1. An integrated circuit (IC) chip, comprising:
- a single set of on-chip baseband correlators serving all channels of a direct sequence spread spectrum (DSSS) communication receiver, wherein said set of on-chip baseband correlators are assigned to a particular GPS signal at a given time or an arbitrary number of different receiver channels;
a carrier NCO for generating corrected local frequencies;
a set of intermediate frequency (IF) signal mixers in communication with said carrier NCO and coupled to said set of on-chip baseband correlators; and
a first memory for storing a plurality of input IF samples on a first-in-first-out (FIFO) basis;
wherein said set of on-chip baseband correlators are configured to process said input IF samples M samples at a time, where M represents number of said input IF samples in one PN sequence.
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Accused Products
Abstract
The present invention provides a new baseband integrated circuit (IC) architecture for direct sequence spread spectrum (DSSS) communication receivers. The baseband IC has a single set of baseband correlators serving all channels in succession. No complex parallel channel hardware is required. A single on-chip code Numerically Controlled Oscillator (NCO) drives a pseudorandom number (PN) sequence generator, generates all code sampling frequencies, and is capable of self-correct through feedback from an off-chip processor. A carrier NCO generates corrected local frequencies. These on-chip NCOs generate all the necessary clocks. This architecture advantageously reduces the total hardware necessary for the receiver and the baseband IC thus can be realized with a minimal number of gate count. The invention can accommodate any number of channels in a navigational system such as the Global Positioning System (GPS), GLONASS, WAAS, LAAS, etc. The number of channels can be increased by increasing the circuit clock speed.
71 Citations
13 Claims
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1. An integrated circuit (IC) chip, comprising:
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a single set of on-chip baseband correlators serving all channels of a direct sequence spread spectrum (DSSS) communication receiver, wherein said set of on-chip baseband correlators are assigned to a particular GPS signal at a given time or an arbitrary number of different receiver channels; a carrier NCO for generating corrected local frequencies; a set of intermediate frequency (IF) signal mixers in communication with said carrier NCO and coupled to said set of on-chip baseband correlators; and a first memory for storing a plurality of input IF samples on a first-in-first-out (FIFO) basis;
wherein said set of on-chip baseband correlators are configured to process said input IF samples M samples at a time, where M represents number of said input IF samples in one PN sequence. - View Dependent Claims (2, 3, 4)
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5. A method of time-sharing a single set of on-chip baseband correlators, wherein said set of on-chip baseband correlators serves all channels of a direct sequence spread spectrum (DSSS) communication receiver, said method comprising the step of:
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a) storing a plurality of samples of down-converted frequency signals in a first memory; b) reading said plurality of samples from said first memory on a first-in-first-out (FIFO) basis; c) multiplying said samples with a carrier signal via separate in-phase (I) and quadrature (Q) channel paths to generate two parallel I and Q signals; d) separately correlating said I and Q signals with identical locally generated replica codes; e) performing said correlating step over a fixed time interval for each DSSS signal received; and f) storing correlation results in a second memory. - View Dependent Claims (6, 7, 8)
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9. A direct sequence spread spectrum (DSSS) communication receiver, comprising:
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an integrated circuit (IC) chip having a single set of on-chip baseband correlators serving all channels of said direct sequence spread spectrum (DSSS) communication receiver; an on-chip code Numerically Controlled Oscillator (NCO) in communication with said set of on-chip baseband correlators;
whereinsaid code NCO drives a pseudorandom number (PN) sequence generator; said code NCO generates all code sampling frequencies; and said code NCO is capable of self-correct through feedback from an off-chip processor; a carrier NCO for generating corrected local frequencies; and a first memory for storing a plurality of input IF samples on a first-in-first-out (FIFO) basis; wherein said set of on-chip baseband correlators are configured to process said input IF samples M samples at a time, where M represents number of said input IF samples in one PN sequence. - View Dependent Claims (10, 11, 12, 13)
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Specification