Method and apparatus for efficient preamble detection in digital data receivers

• US 7,428,273 B2
• Filed: 09/16/2004
• Issued: 09/23/2008
• Est. Priority Date: 09/18/2003
• Status: Expired due to Fees

• Current Assignee: Promptu Systems Corporation
• Original Assignee: Promptu Systems Corporation
• Inventors: Foster, Mark J.
• Primary Examiner(s): WANG, TED M
• Application Number:
  US10/944,503
• Publication Number:
  US 20050063493A1
• Time in Patent Office: 1,468 Days
• Field of Search: 375/329, 375/308, 375/279, 375/324, 375/325, 375/340
• US Class Current: 375/329
• CPC Class Codes: H04L 27/227 using coherent demodulation

Abstract

Traditional techniques for data reception in burst-mode receivers are of significant complexity. To aid detection, most burst-mode systems transmit a preamble, or predetermined data pattern, at the start of each new block of data. Using current methods, the detection of a new preamble, indicating the arrival of a new burst of data, is particularly complex. A method and apparatus is disclosed that significantly reduces this detection complexity, while maintaining superior signaling performance. This simplification can lead to higher data throughput within processing-limited receivers, and/or a greater degree of parallelism in multiple channel receivers.

Claims

1. A preamble detector for QPSK, comprising:

an input for receiving digitized input I and Q samples, wherein said input I and Q samples represent a reconstructed base band form of QPSK modulation;

a carrier derotation means for aligning said incoming signal phases with I and Q axes;

sign means for producing a ‘

1’

if said I and Q samples are greater than or equal to 0, or a ‘

0’

if said samples are less than 0;

sample delay means for providing chains of N-sample delays to yield one symbol-length delay for both I and Q;

a differential decoder for combining a current symbol state with a prior symbol state to yield a differentially decoded symbol value;

a multiplexer for alternating between a least-significant and a most-significant bit of said differentially decoded symbol values; and

a preamble shift register containing a serial-sequential representation of a received data stream.

2. The detector of claim 1:

wherein said shift register length is twice a number of bits in a preamble; and

wherein binary data bits are clocked into said preamble shift register at two bits/sample.

3. The detector of claim 2, said shift register further comprising:

XOR means for locating a unique preamble data pattern in accordance with the following;

Preamble_Mismatch=Preamble_Register XOR PREAMBLE_PATTERN

wherein said PREAMBLE_PATTERN is a bit-pair doubled representation of a unique data pattern that defines an implementation-specific value for said preamble;

wherein Preamble_Mismatch indicates outputs of said XOR means;

wherein said XOR means invert any bits in said preamble that should be a binary ‘

1;

’ and

wherein when outputs of said XOR means all become zero, indicating no mismatch, a data pattern has been identified that matches a desired preamble data pattern.

4. The detector of claim 3, further comprising:

means for producing a value of modulation power, where;

power_k=abs(real(R_k)·

real(R_k-N))+abs(imag(R_k)·

imag(R_k-N)).

5. The detector of claim 3, further comprising:

a comparator for comparing said signal power level to a predetermined minimum acceptable power threshold;

wherein an output of said comparator is a ‘

1’

if an input signal level is too low to be considered a valid transmission, and said comparator output is ‘

0’

if said power level exceeds said threshold;

a Power_Invalid shift register which receives said comparator output, said Power_Invalid shift register containing a history of an invalidity status of recent samples; and

OR means for merging Power_Invalid flags with Preamble_Mismatch outputs, resulting in a product expression of;

Preamble_Status=Preamble_Mismatch OR Power_Invalid

wherein a candidate preamble has both a proper bit polarity and a proper signal level; and

wherein said OR means combine said I and Q data bits, whereby if either of said I or Q samples have incorrect signs, then an output of that sample from said OR means becomes true to indicate a non-matching symbol.

6. The detector of claim 5, further comprising:

AND means for isolating N-1 out of N samples to ignore one sample/symbol during which zero-crossings may occur;

wherein with two samples/symbol, said AND means isolates alternate samples.

7. The detector of claim 6, further comprising:

NOR means;

wherein once all relevant samples have proper signs, and have been received with a sufficient power level, an output of said NOR means is driven high, indicating Preamble_Found;

wherein said detector begins the process of receiving a new data burst.

8. The detector of claim 1, wherein, if a preamble used is an unchanging constant, said detector further comprising:

NOT means inserted selectively at any sample timing offset where an expected value of a preamble is ‘

1.’

9. The detector of claim 1, wherein said shift register is extendable to use said detector with any integer number of samples/symbol, or any preamble length.

10. A preamble detection method for QPSK, comprising the steps of:

receiving digitized input I and Q samples, wherein said input I and Q samples represent a reconstructed base band form of QPSK modulation;

aligning said incoming signal phases with I and Q axes;

producing a ‘

1’

if said I and Q samples are greater than or equal to 0, or a ‘

0’

if said samples are less than 0;

providing chains of N-sample delays to yield one symbol-length delay for both I and Q;

combining a current symbol state with a prior symbol state to yield a differentially decoded symbol value;

alternating between a least-significant and a most-significant bit of said differentially decoded symbol values; and

providing a serial-sequential representation of a received data stream.

11. The detection method of claim 10:

wherein said serial-sequential representation of a received data stream length is twice a number of bits in a preamble; and

wherein binary data bits are clocked in at two bits/sample.

12. The detection method of claim 11, further comprising the step of:

locating a unique preamble data pattern in accordance with the following;

Preamble_Mismatch=Preamble_Register XOR PREAMBLE_PATTERN

wherein said PREAMBLE_PATTERN is a bit-pair doubled representation of a unique data pattern that defines an implementation-specific value for said preamble;

wherein Preamble_Mismatch indicates an XOR output;

wherein any bits in said preamble that should be a binary ‘

1’

are inverted; and

wherein when said XOR output becomes zero, indicating no mismatch, a data pattern has been identified that matches a desired preamble data pattern.

13. The detection method of claim 12, further comprising the step of:

implementing a power estimation function;

producing a value of modulation power, where;

power_k=abs(real(R_k)·

real(R_k-N))+abs(imag(R_k)·

imag(R_k-N)).

14. The detection method of claim 12, further comprising the steps of:

comparing said signal power level to a predetermined minimum acceptable power threshold;

wherein an output of said comparing step is a ‘

1’

if an input signal level is too low to be considered a valid transmission, and said comparing step output is ‘

0’

if said power level exceeds said threshold;

receiving said comparing step output a Power_Invalid shift register, said Power_Invalid shift register containing a history of an invalidity status of recent samples; and

merging Power_Invalid flags with Preamble_Mismatch outputs, resulting in a product expression of;

Preamble_Status=Preamble_Mismatch OR Power_Invalid

wherein a candidate preamble has both a proper bit polarity and a proper signal level; and

wherein said merging step combines said I and Q data bits, whereby if either of said I or Q samples have incorrect signs, then an output of that sample from said merging step becomes true to indicate a non-matching symbol.

15. The detection method of claim 14, further comprising the step of:

isolating N-1 out of N samples to ignore one sample/symbol during which zero-crossings may occur;

wherein with two samples/symbol, alternate samples are isolated.

16. The detection method of claim 15, wherein once all relevant samples have proper signs, and have been received with a sufficient power level, an output is driven high, indicating Preamble_Found;

wherein said detector begins the process of receiving a new data burst.

17. The detection method of claim 10, wherein, if a preamble used is an unchanging constant, said detector further comprising the step of:

inserting a NOT function selectively at any sample timing offset where an expected value of a preamble is ‘

1.’

18. The detection method of claim 10, further comprising the step of:

extending said detector with any integer number of samples/symbol, or any preamble length.