Array substrate for in-plane switching liquid crystal display device with polycrystalline silicon pixel electrode and method of manufacturing the same

• US 7,430,034 B2
• Filed: 09/27/2006
• Issued: 09/30/2008
• Est. Priority Date: 03/20/2003
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Jeoung, Hun
• Primary Examiner(s): Kim; Richard H
• Application Number:
  US11/527,552
• Publication Number:
  US 20070013820A1
• Time in Patent Office: 734 Days
• Field of Search: 349/140, 349/141
• US Class Current: 349/141
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136213 Storage capacitors associated with the pixel electrode
• CPC Class Codes: G02F 2201/40 Arrangements for improving the aperture ratio

Abstract

An array substrate for in-plane switching liquid crystal display device includes a gate line on a substrate, a data line crossing the gate line to define a pixel region, a semiconductor layer including an active area and a source area, wherein the active area overlaps the gate line and the source area overlaps the data line, a drain electrode connected to the semiconductor layer, a first capacitor electrode in the pixel region and connected to the drain electrode, a pixel electrode connected to the first capacitor electrode and substantially in parallel to the data line, a common line substantially parallel to the gate line, a second capacitor electrode connected to the common line and overlapping the first capacitor electrode, and a common electrode connected to the common line and alternatively arranged with the pixel electrode, wherein the source area of the semiconductive layer, the drain electrode, the first capacitor electrode and the pixel electrode include doped polycrystalline silicon.

Claims

1. An array substrate for an in-plane switching liquid crystal display device, comprising:

a gate line on a substrate;

a data line crossing the gate line to define a pixel region;

a semiconductor layer including an active area and a source area, wherein the active area overlaps the gate line and the source area overlaps the data line;

a drain electrode connected to the semiconductor layer;

a first capacitor electrode in the pixel region and connected to the drain electrode;

a pixel electrode connected to the first capacitor electrode and substantially in parallel to the data line;

a common line substantially parallel to the gate line;

a second capacitor electrode connected to the common line and overlapping the first capacitor electrode; and

a common electrode connected to the common line and alternatively arranged with the pixel electrode,

wherein the source area of the semiconductor layer, the drain electrode, the first capacitor electrode and the pixel electrode include doped polycrystalline silicon.

2. The array substrate of claim 1, wherein the semiconductor layer, the drain electrode, the first capacitor electrode and the pixel electrode are formed to be substantially integrated.

3. The array substrate of claim 1, further comprising a gate insulating layer under the gate line and the common line.

4. The array substrate of claim 3, wherein the first and second capacitor electrodes form a storage capacitor having the gate insulating layer interposed therebetween.

5. The array substrate of claim 1, further comprising an inter insulating layer covering a thin film transistor, the thin film transistor including the semiconductor layer, a gate electrode, a source electrode and the drain electrode.

6. The array substrate of claim 5, wherein the inter insulating layer includes a source contact hole to expose the source area of the semiconductor layer, and the source electrode being connected to the semiconductor layer via the source contact hole.

7. The array substrate of claim 1, wherein the semiconductor layer is patterned using dry etching.