Techniques for optimizing design of a hard intellectual property block for data transmission
First Claim
1. A programmable logic integrated circuit comprising a hard intellectual property (HIP) block designed to transmit data along parallel data channels, the hard intellectual property block comprising:
- an oversampler that reduces clock skew between a clock signal and data in a first set of parallel data channels;
a down converter coupled to the oversampler that converts the data from the first set of parallel data channels to a second set of parallel data channels that have less parallel data channels than the first set; and
a channel alignment block coupled to the down converter that aligns corresponding data bits on the second set of parallel data channels.
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Abstract
Techniques are provided for implementing channel alignment for a data transmission interface in an HIP block on a programmable logic integrated circuit. The HIP block channel alignment logic can be run using a reduced number of parallel data paths, which consumes substantially less logic resources. Also, the HIP block channel alignment logic circuits can be processed at the higher HIP core clock rate in serial, decreasing lock latency time. Techniques are provided for implementing error handling for transmitted data in programmable logic circuits. The programmable logic circuits can be configured to implement error generation and error monitoring functions that are tailored for any application. Alternatively, the logic elements can be configured to perform other functions for applications that do not require error handling. The phase skew between data and clock signals on an integrated circuit are reduced by routing clock signals along with the data signals to each circuit block.
32 Citations
15 Claims
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1. A programmable logic integrated circuit comprising a hard intellectual property (HIP) block designed to transmit data along parallel data channels, the hard intellectual property block comprising:
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an oversampler that reduces clock skew between a clock signal and data in a first set of parallel data channels; a down converter coupled to the oversampler that converts the data from the first set of parallel data channels to a second set of parallel data channels that have less parallel data channels than the first set; and a channel alignment block coupled to the down converter that aligns corresponding data bits on the second set of parallel data channels. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method for performing channel alignment on a hard intellectual property (HIP) block of a programmable logic integrated circuit, the HIP block designed to transmit data along parallel data channels, the method comprising:
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oversampling a clock signal to reduce clock skew between the clock signal and the data received on a first set of parallel data channels; converting the data on the first set of parallel data channels to a second set of parallel data channels that have less parallel data channels than the first set; and aligning corresponding data bits in the second set of parallel data channels using channel alignment circuitry in the HIP block. - View Dependent Claims (11, 12, 13, 14, 15)
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Specification