Regenerative clock repeater

• US 7,436,232 B2
• Filed: 09/17/2003
• Issued: 10/14/2008
• Est. Priority Date: 06/17/2003
• Status: Active Grant

• Current Assignee: Nera Innovations Limited (Atlantic IP Services Limited)
• Original Assignee: Atmel Corporation (Microchip Technology Incorporated)
• Inventors: Sivero, Stefano, Frulio, Massimiliano
• Primary Examiner(s): COX, CASSANDRA F
• Application Number:
  US10/666,142
• Publication Number:
  US 20040257131A1
• Time in Patent Office: 1,854 Days
• Field of Search: None
• US Class Current: 327/165
• CPC Class Codes: G06F 1/10 Distribution of clock signals , e.g. skew
• CPC Class Codes: H03K 19/01721 by means of a pull-up or down element

Abstract

A regenerative clock repeater comprises an edge detector and an output driver means to produce the clock signal by recovering its high logical level and low logical level. The output driver means further comprises a pull-up and a pull-down circuitry adapted to receive a pair of control signals. These control signals are generated by the edge detector to sense the rising edge and falling edge of the clock signal. Inside the edge detector, a pair of threshold level detectors detect a high and a low logical level of the clock signal and inputs the results to a combination of logic gates and a latch to keep the locations of the signal markers fixed. These fixed-location of control signals trigger the output driver means to recover the high logical level and the low logical level of said clock signal.

Claims

1. A clock repeater for regenerating a clock signal on a clock distribution line, comprising:

an edge detector means for sensing a rising edge and a falling edge of said clock signal and generating respective pull-up and pull-down control signals in response thereto; and

an output driver means, connected to said edge detector means to receive said control signals therefrom, for recovering high and low logical levels of said clock signal;

wherein said edge detector means further comprises;

a level detector means for generating a first signal and a second signal by detecting a rise edge from a low logical level and a fall edge from a high logical level of said clock signal;

a first logic NOR gate adapted to receive an inverse of the first signal and an inverse of the second signal;

a second logic NOR gate adapted to receive the first signal and the second signal;

a set/reset latch coupled to an output of the first logic NOR gate at a set input terminal, and an output of the second logic NOR gate at the reset input terminal to produce a third signal;

a first logic NAND gate adapted to receive the first signal, the inverse of the second signal and the third signal to generate the pull-up control signal; and

a third logic NOR gate adapted to receive the inverse of the first signal, the second signal, and the third signal to generate the pull-down control signal.

2. The clock repeater of claim 1, wherein said level detector means further comprises a first level detector means for detecting said high logical level and a second level detector means for detecting said low logical level of said clock signal.

3. The clock repeater of claim 2, wherein said first level detector means further comprising:

a low-threshold PMOS transistor and a high-threshold NMOS transistor for detecting said high logical level of said clock signal, wherein the gate of said low-threshold PMOS transistor and the gate of said high-threshold NMOS transistor being coupled together and to said clock signal, the drain of said low-threshold PMOS transistor being coupled to the drain of the high-threshold NMOS transistor, the source of said low-threshold PMOS being coupled to a supply voltage, and the source of said high-threshold NMOS transistor being coupled to an electrical ground; and

a first inverter having an input terminal coupled to the drain-drain junction of said low-threshold PMOS transistor and said high-threshold NMOS transistor to produce the said first signal, wherein the output terminal of said first inverter being the inverse of said first signal.

4. The clock repeater of claim 2, wherein said second level detector means further comprises:

a high-threshold PMOS transistor and a low-threshold NMOS transistor for detecting said low logical levels of said clock signal, wherein the gate of said high-threshold PMOS transistor and the gate of said low-threshold NMOS transistor being coupled together, the drain of said high-threshold PMOS transistor being coupled to the drain of the low-threshold NMOS transistor, the source of said high-threshold PMOS transistor being coupled to said supply voltage, and the source of said low-threshold NMOS transistor being coupled to said electrical ground; and

a second inverter having an input terminal coupled to the drain-drain junction of the high-threshold PMOS transistor and said low-threshold NMOS transistor to produce said second signal, wherein the output terminal of said second inverter being the inverse of said second signal.

5. A clock repeater for regenerating a clock signal on a clock distribution line, comprising:

an edge detector means for sensing a rising edge and a falling edge of said clock signal and generating respective pull-up and pull-down control signals in response thereto; and

an output driver means, connected to said edge detector means to receive said control signals therefrom, for recovering high and low logical levels of said clock signal;

wherein said output driver means further comprises;

a pull-up PMOS transistor;

a NMOS pull-down transistor coupled to said pull-up PMOS transistor, wherein the gate of the said PMOS pull-up transistor being coupled to said pull-up control signal, the drain of said pull-up PMOS transistor being coupled to the drain of the NMOS pull-down transistor and to said clock signal, the source of the PMOS pull-up transistor being coupled to said voltage supply, a gate of the NMOS pull-down transistor being coupled to said pull-down control signal, and the source of said pull-down NMOS transistor coupled to said electrical ground.

6. A clock repeater for regenerating a clock signal on a clock distribution line, comprising:

(a) an edge detector means for sensing a rising edge and a falling edge of said clock signal and generating respective pull-up and pull-down control signals in response thereto, the edge detector means including;

(i) a level detector means for generating a first signal and a second signal by detecting a low logical level and a high logical level of said clock signal;

(ii) a first logic NOR gate adapted to receive an inverse of the first signal and an inverse of the second signal;

(iii) a second logic NOR gate adapted to receive the first signal and a second signal;

(iv) a set/reset latch coupled to the output of the first logic NOR gate at a set input terminal, and the output of the second logic NOR gate at the reset input terminal to produce a third signal;

(v) a first logic NAND gate adapted to receive the first signal, the inverse of the second signal and the third signal to generate the pull-up control signal; and

(vi) a third logic NOR gate adapted to receive the inverse of the first signal, the second signal, and the third signal to generate the pull-down signal; and

(b) an output driver means, connected to said edge detector means to receive said control signals therefrom, for recovering high and low logical levels of said clock signal, the output driver means including;

(i) a pull-up PMOS transistor;

(ii) a NMOS pull-down transistor coupled to said pull-up PMOS transistor, wherein the gate of the said PMOS pull-up transistor being coupled to said pull-up control signal, the drain of said pull-up PMOS transistor being coupled to the drain of the NMOS pull-down transistor and to said input clock signal, the source of the PMOS pull-up transistor being coupled to said voltage supply, a gate of the NMOS pull-down transistor being coupled to said pull-down control signal, and the source of said pull-down NMOS transistor coupled to said electrical ground.

7. The clock repeater of claim 6, wherein said level detector means further comprises a first level detector means for detecting said high logical level and a second level detector means for detecting said low logical level of said clock signal.

8. The clock repeater of claim 7, wherein said first level detector means further comprising:

a low-threshold PMOS transistor and a high-threshold NMOS transistor for detecting said high logical level of said clock signal, wherein the gate of said low-threshold PMOS transistor and the gate of said high-threshold NMOS transistor being coupled together and to said clock signal, the drain of said low-threshold PMOS transistor being coupled to the drain of the high-threshold NMOS transistor, the source of said low-threshold PMOS being coupled to a supply voltage, and the source of said high-threshold NMOS transistor being coupled to an electrical ground; and

a first inverter having an input terminal coupled to the drain-drain junction of said low-threshold PMOS transistor and said high-threshold NMOS transistor to produce the said first signal, wherein the output terminal of said first inverter being the inverse of said first signal.

9. The regenerative clock repeater of claim 7, wherein said second level detector means further comprises:

a high-threshold PMOS transistor and a low-threshold NMOS transistor for detecting said low logical levels of said clock signal, wherein the gate of said high-threshold PMOS transistor and the gate of said low-threshold NMOS transistor being coupled together, the drain of said high-threshold PMOS transistor being coupled to the drain of the low-threshold NMOS transistor, the source of said high-threshold PMOS transistor being coupled to said supply voltage, and the source of said low-threshold NMOS transistor being coupled to said electrical ground; and

a second inverter having an input terminal coupled to the drain-drain junction of the high-threshold PMOS transistor and said low-threshold NMOS transistor to produce said second signal, wherein the output terminal which is the inverse of said second signal.

10. A synchronous semiconductor memory device, comprising:

a memory cell array including a plurality of memory cells arranged in rows and columns;

a data input/output terminal;

a control circuit controlling operations of said synchronous semiconductor memory device;

a sensing and writing circuit;

a row/column address decoder for selecting rows and columns of said memory cell array; and

a clock circuit for synchronizing said operations of said synchronous semiconductor memory device, wherein said clock circuit comprises a plurality of regenerative clock circuits distributed along clock lines within said memory device, each of which further comprises;

(a) an edge detector means for sensing a rising edge and a falling edge of said clock signal and generating respective pull-up and pull-down control signals in response thereto, the edge detector means including;

(i) a level detector means for generating a first signal and a second signal by detecting a low logical level and a high logical level of said clock signal;

(ii) a first logic NOR gate adapted to receive an inverse of the first signal and an inverse of the second signal;

(iii) a second logic NOR gate adapted to receive the first signal and a second signal;

(iv) a set/reset latch coupled to an output of the first logic NOR gate at a set input terminal, and an output of the second logic NOR gate at the reset input terminal to produce a third signal;

(v) a first logic NAND gate adapted to receive the first signal, the inverse of the second signal and the third signal to generate the pull-up control signal; and

(vi) a third logic NOR gate adapted to receive the inverse of the first signal, the second signal, and the third signal to generate the pull-down control signal;

(b) an output driver means, connected to said edge detector means to receive said control signals therefrom, for recovering high and low logical levels of said clock signal, the output driver means including;

(i) a pull-up PMOS transistor;

(ii) a NMOS pull-down transistor coupled to said pull-up PMOS transistor, wherein the gate of the said PMOS pull-up transistor being coupled to said pull-up control signal, the drain of said pull-up PMOS transistor being coupled to the drain of the NMOS pull-down transistor and to said input clock signal, the source of the PMOS pull-up transistor being coupled to said voltage supply, a gate of the NMOS pull-down transistor being coupled to said pull-down control signal, and the source of said pull-down NMOS transistor coupled to said electrical ground.

11. The synchronous semiconductor memory device of claim 10, wherein said level detector means further comprises a first level detector means for detecting said high logical level and a second level detector means for detecting said low logical level of said clock signal.

12. The synchronous semiconductor memory device 11, wherein said first level detector means further comprising:

a low-threshold PMOS transistor and a high-threshold NMOS transistor for detecting said high logical level of said clock signal, wherein the gate of said low-threshold PMOS transistor and the gate of said high-threshold NMOS transistor being coupled together and to said clock signal, the drain of said low-threshold PMOS transistor being coupled to the drain of the high-threshold NMOS transistor, the source of said low-threshold PMOS being coupled to a supply voltage, and the source of said high-threshold NMOS transistor being coupled to an electrical ground; and

a first inverter having an input terminal coupled to the drain-drain junction of said low-threshold PMOS transistor and said high-threshold NMOS transistor to produce the said first signal, wherein the output terminal of said first inverter being the inverse of said first signal.

13. The synchronous semiconductor memory device 6, wherein said second level detector means further comprises:

a high-threshold PMOS transistor and a low-threshold NMOS transistor for detecting said low logical levels of said clock signal, wherein the gate of said high-threshold PMOS transistor and the gate of said low-threshold NMOS transistor being coupled together, the drain of said high-threshold PMOS transistor being coupled to the drain of the low-threshold NNOS transistor, the source of said high-threshold PMOS transistor being coupled to said supply voltage, and the source of said low-threshold NMOS transistor being coupled to said electrical ground; and

a second inverter having an input terminal coupled to the drain-drain junction of the high-threshold PMOS transistor and said second low-threshold NMOS transistor to produce said second signal, wherein the output terminal which is the inverse of said second signal.

14. A method for regenerating a clock signal in a synchronous semiconductor memory, such method comprises the following steps:

detecting a rise edge from a low logical level and a fall edge from a high logical level of said clock signal;

generating a pull-up control signal in response to the detecting of the rise edge of the clock signal;

generating a pull-down control signal in response to the detecting of the fall edge of said clock signal;

recovering said high logical level using the pull-up control signal; and

recovering said low logical level using the pull-down control signal.

15. The method of claim 14 wherein the step of generating the pull-up control signal further comprises the steps of:

generating a first signal based on the high logical level;

generating a second signal based on the low logical level; and

generating a third signal using the first and the second signal and their complementary signals.

16. A clock repeater for regenerating a clock signal on a clock distribution line, comprising:

an edge detector means for sensing a rising edge and a falling edge of the clock signal and generating respective pull-up and pull-down control signals in response thereto, the edge detector means having

a level detector means for generating a first signal and a second signal by detecting a rising edge from a low logical level and a falling edge from a high logical level of the clock signal; and

a first logic circuit configured to receive the first signal, an inverse of the second signal, and a third signal based upon the first and second signals to generate the pull-up control signal;

a latch coupled to the edge detector and configured to produce the third signal; and

an output driver coupled to the edge detector and configured to receive control signals from the edge detector and recover high and low logic levels of the clock signal.

17. The clock repeater of claim 16 further comprising:

a second logic circuit configured to receive an inverse of the first signal and the inverse of the second signal;

a third logic circuit configured to receive the first signal and the second signal; and

a fourth logic circuit configured to receive the inverse of the first signal, the second signal, and the third signal to generate the pull-down control signal.

18. The clock repeater of claim 17 wherein the latch is coupled to an output of the second logic circuit at a first input terminal and to an output of the third logic circuit at a second input terminal and is configured to produce the third signal.

19. A clock repeater to regenerate a clock signal on a clock distribution line, comprising:

an edge detector configured to generate respective pull-up and pull-down control signals based on sensing a rising edge and a falling edge of the clock signal, the edge detector having

a level detector configured to generate a first signal and a second signal by detecting a rising edge from a low logical level and a falling edge from a high logical level of the clock signal; and

a first logic circuit configured to receive the first signal, an inverse of the second signal, and a third signal based upon the first and second signals to generate the pull-up control signal;

a latch coupled to the edge detector and configured to produce the third signal; and

an output driver coupled to the edge detector and configured to receive control signals from the edge detector and recover high and low logic levels of the clock signal.

20. The clock repeater of claim 19 further comprising:

a second logic circuit configured to receive an inverse of the first signal and the inverse of the second signal;

a third logic circuit configured to receive the first signal and the second signal; and

a fourth logic circuit configured to receive the inverse of the first signal, the second signal, and the third signal to generate the pull-down control signal.

21. The clock repeater of claim 20 wherein the latch is coupled to an output of the second logic circuit at a first input terminal and to an output of the third logic circuit at a second input terminal and is configured to produce the third signal.