DC-DC converter and method

• US 7,439,716 B2
• Filed: 09/12/2006
• Issued: 10/21/2008
• Est. Priority Date: 09/12/2006
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Inventors: Gay, Michael John
• Primary Examiner(s): Riley; Shawn
• Application Number:
  US11/530,983
• Publication Number:
  US 20080062733A1
• Time in Patent Office: 770 Days
• Field of Search: 323/224, 323/225, 323/283
• US Class Current: 323/224
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators

Abstract

A DC-DC converter and method for compensating for errors in the DC-DC converter. The DC-DC converter includes an inductor coupled for receiving a source of operating voltage through a plurality of switches. The switches are controlled by a control circuit that has first and second circuit paths that are substantially parallel to each other. Each circuit path is comprised of two switched capacitor comparators that are connected in series. The circuit paths function such that during one portion of a clock period one of the circuit paths operates in an error correction mode and the other circuit path operates in a normal mode. During a different portion of the clock period the operational modes of the circuit paths switch. This allows for a calibration interval in a sampled system in which at least one circuit path is always active and responsive to the input signals in a desired manner.

Claims

1. A method for compensating errors in a DC-DC converter, comprising:

providing a first signal path having at least one circuit element;

providing a second signal path having at least one circuit element; and

switching one of the first or second signal paths into an error correction mode to compensate for errors in the at least one circuit element in the first or second signal path that is in the error correction mode, wherein the other signal path of the first or second signal path is in a normal operating mode.

2. The method of claim 1, further including switching the one of the first or second signal paths into the error correction mode during a first part of a first clock period and switching the one of the first or second signal paths into the normal mode during a second part of the first clock period.

3. The method of claim 2, wherein the second part of the first clock period is a remaining portion of the first clock period.

4. The method of claim 3, wherein switching the one of the first or second signal paths into the normal mode further includes switching the one of the first or second signal paths into the normal mode during the whole of the second clock period.

5. The method of claim 4, further including selecting output signals from the at least one element of the first or second signal paths during the second clock period.

6. The method of claim 1, further including using a difference between a load voltage and a reference voltage to generate an output signal.

7. The method of claim 1, further including:

integrating signals derived from input signals to the first signal path to produce a first integrated signal;

integrating signals derived from input signals to the second signal path to produce a second integrated signal; and

generating first and second comparator output signal components from the first and second integrated signals.

8. The method of claim 7, further including:

generating a first control path signal by comparing the first comparator output signal with a charge indication signal that is indicative a charge supplied to a load during a concurrent clock period; and

generating a second control path signal by comparing the second comparator output signal with the charge indication signal that is indicative the charge supplied to a load during the concurrent clock period.

9. The method of claim 8, further including using the first and second control path signals to generate an output voltage for communicating with a plurality of switches.

10. The method of claim 8, further including:

discharging a first energy storage element at a beginning of each clock period; and

charging the first energy storage element with a first current, wherein the first current is proportional to a second current that flows through a second energy storage element, and wherein the charge indication signal that is indicative of the charge supplied to a load during the concurrent clock period is a voltage developed across the first energy storage element.

11. The method of claim 10, further including providing a third current that is combined with the current that is proportional to the second current, wherein the third current inhibits development of an oscillatory mode.

12. A method of correcting for offset error in a DC-DC converter, comprising:

generating a first signal in response to a reference signal and a converter output signal, the first signal comprising a first sub-signal and a second sub-signal;

generating a second signal in response to the reference signal and the converter output signal, the second signal comprising a third sub-signal and a fourth sub-signal;

correcting a first offset error in the first signal during a first period of a clock signal; and

correcting a second offset error in the second signal during a second period of the clock signal, the first and second periods being different periods.

13. The method of claim 12, wherein the second period follows the first period.

14. The method of claim 12, wherein generating the first signal comprises:

attenuating and filtering the reference signal and the converter output signal;

comparing the attenuated and filtered reference signal with the attenuated and filtered converter output signal to generate the first sub-signal, wherein comparing the attenuated and filtered reference and converter output signals includes introducing a first offset error correction signal into the first sub-signal;

comparing the first sub-signal with an internal reference voltage to generate the second sub-signal, wherein comparing the first sub-signal with the internal reference signal includes introducing a second offset error correction signal into the second sub-signal.

15. The method of claim 14, wherein generating the second signal comprises:

attenuating and filtering the reference signal and the converter output signal;

comparing the attenuated and filtered reference signal with the attenuated and filtered converter output signal to generate the third sub-signal, wherein comparing the attenuated and filtered reference and converter output signals includes introducing a third offset error correction signal into the third sub-signal; and

comparing the third sub-signal with the internal reference voltage to generate the fourth sub-signal, wherein comparing the third sub-signal with the internal reference signal includes introducing a fourth offset error correction signal into the fourth sub-signal.

16. The method of claim 15, further including:

selecting one of the first signal or the second signal to generate a selected signal;

generating a driver signal from the selected signal;

using the driver signal to create an image current; and

using the image current to generate the internal reference signal.

17. The method of claim 16, wherein using the driver signal to create the image current includes turning on first and second transistors, wherein the image current is an image of the current flowing through the first transistor.

18. A DC-DC converter, comprising:

a control circuit having a plurality of inputs and a plurality of outputs, wherein the control circuit comprises;

a first circuit path having first and second inputs and an output; and

a second circuit path having first and second inputs and an output, wherein the first and second circuit paths cooperate to provide offset cancellation of errors in elements of the first and second circuit paths; and

a switching network coupled to the control circuit.

19. The DC-DC converter of claim 18, further including a clock generator coupled to the control circuit and to the switching network.

20. The DC-DC converter of claim 18, wherein a portion of the elements in the first circuit path comprises switched capacitors.

21. The DC-DC converter of claim 19, wherein a portion of the elements in the second circuit path comprises switched capacitors.

22. The DC-DC converter of claim 18, wherein a portion of the elements in the first circuit path operate in an error correction mode during a first portion of a first clock period.

23. The DC-DC converter of claim 22, wherein a portion of the elements in the first circuit path operate in a normal mode during a second portion of the first clock period.

24. The DC-DC converter of claim 18, wherein the first circuit path comprises a first comparator that produces an output responsive to a difference between a portion of a load voltage and a reference voltage.

25. The DC-DC converter of claim 24, wherein the second circuit path comprises a second comparator that produces an output responsive to a difference between a portion of a load voltage and a reference voltage.

26. The DC-DC converter of claim 25, wherein the first and second comparators include a filter means for doting the first and second circuit paths, respectively.

27. The DC-DC converter of claim 26, wherein the filter means includes an integrator for providing an output signal component common to the first and second circuit paths.

28. The DC-DC converter of claim 25, wherein the first circuit path further includes a third comparator coupled to the first comparator and the second circuit path further includes a fourth comparator coupled to the second comparator.

29. The DC-DC converter of claim 18, further including a capacitor coupled to the switching network.