Network-processor accelerator
First Claim
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1. A network apparatus comprising:
- a network interface for transmitting and receiving packets to and from a network;
a network processor for transferring the received packets to a next transfer destination;
a table memory for storing a table referred for the transfer of packets; and
a network-processor accelerator for transferring the received packets;
wherein the network-processor accelerator transfers the received packets having the destination addresses which are identical to that of the received packets already processed with the network processor, andwherein the network-processor accelerator, comprises;
an interface unit for temporarily storing the received packet;
a packet analysis unit for obtaining the extracted information by extracting the necessary domain from the received packets;
a cache memory for storing the process result required for transfer process of the received packets;
an address generation means for referring to the cache memory from the extracted information;
a means for determining whether the relevant information exists or not in the cache memory as the result of reference to the cache memory from the extracted information;
a means for reassembling the packets from the relevant information when the relevant information exists in the cache memory;
a primary table for management of the packets as cache miss packets when the relevant information does not exist in the cache memory;
a secondary table for management of the second and subsequent packets that are containing the relevant information not existing in the cache memory and are expected to provide the process result which is identical to that of the packets recorded in the primary table;
an interface unit for transmitting the packets and necessary information to the network processor for implementing, with a programmable manner, the processes of cache miss packet recorded to the primary table;
an interface unit for receiving the processed packets and added information from the network processor;
a means for recording the process result information of the processed packets to the cache memory;
a means for applying the process result to the relevant packets recorded to the secondary table;
a means for releasing the entries of the primary and secondary tables having completed the processes;
a means for generating the transmitting packets from the processed packets or the process result information; and
an interface unit for transmitting the processed packets.
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Abstract
In order to perform cache processing for the received packets, a network apparatus is provided with a network-processor accelerator for caching the process result of a network processor. Accordingly, the network apparatus of the present invention ensuring higher packet-processing throughput can be realized by improving the packet-processing throughput without increase in the chip area, increase in the power consumption, and shortage in an external connected memory bandwidth.
12 Citations
25 Claims
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1. A network apparatus comprising:
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a network interface for transmitting and receiving packets to and from a network; a network processor for transferring the received packets to a next transfer destination; a table memory for storing a table referred for the transfer of packets; and a network-processor accelerator for transferring the received packets; wherein the network-processor accelerator transfers the received packets having the destination addresses which are identical to that of the received packets already processed with the network processor, and wherein the network-processor accelerator, comprises; an interface unit for temporarily storing the received packet; a packet analysis unit for obtaining the extracted information by extracting the necessary domain from the received packets; a cache memory for storing the process result required for transfer process of the received packets; an address generation means for referring to the cache memory from the extracted information; a means for determining whether the relevant information exists or not in the cache memory as the result of reference to the cache memory from the extracted information; a means for reassembling the packets from the relevant information when the relevant information exists in the cache memory; a primary table for management of the packets as cache miss packets when the relevant information does not exist in the cache memory; a secondary table for management of the second and subsequent packets that are containing the relevant information not existing in the cache memory and are expected to provide the process result which is identical to that of the packets recorded in the primary table; an interface unit for transmitting the packets and necessary information to the network processor for implementing, with a programmable manner, the processes of cache miss packet recorded to the primary table; an interface unit for receiving the processed packets and added information from the network processor; a means for recording the process result information of the processed packets to the cache memory; a means for applying the process result to the relevant packets recorded to the secondary table; a means for releasing the entries of the primary and secondary tables having completed the processes; a means for generating the transmitting packets from the processed packets or the process result information; and an interface unit for transmitting the processed packets. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A network apparatus comprising:
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a network interface for transmitting or receiving packets to a network; a first processor for transferring the received packets to a next transfer destination; a table memory for storing a table referred for the transfer process; and a second processor for transferring the received packets, wherein the second processor transfers the received packets having the destination addresses which are identical to that of the received packets already processed with the first processor, and the second processor comprises; an interface unit for temporarily storing the received packet; a packet analysis unit for obtaining the extracted information by extracting the necessary domain from the received packets; a cache memory for storing the process result required for transfer process of the received packets; an address generation means for referring to the cache memory from the extracted information; a means for determining whether the relevant information exists or not in the cache memory as the result of reference to the cache memory from the extracted information; a means for reassembling the packets from the relevant information when the relevant information exists in the cache memory; a primary table for management of the packets as cache miss packets when the relevant information does not exist in the cache memory; a secondary table for management of the second and subsequent packets that are containing the relevant information not existing in the cache memory and are expected to provide the process result which is identical to that of the packets recorded in the primary table; an interface unit for transmitting the packets and necessary information to the first processor for implementing, with a programmable manner, the processes of cache miss packet recorded to the primary table; an interface unit for receiving the processed packets and added information from the first processor; a means for recording the process result information of the processed packets to the cache memory; a means for applying the process result to the relevant packets recorded to the secondary table; a means for releasing the entries of the primary and secondary tables having completed the processes; a means for generating the transmitting packets from the processed packets or the process result information; and an interface unit for transmitting the processed packets.
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17. A network-processor accelerator, comprising:
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an input interface unit for receiving packets; a packet memory for temporarily storing the received packets; a packet analysis unit for obtaining the extracted information by extracting the necessary domain from the received packets; a cache memory for storing result of processes required for the transfer process of the received packets; a means for determining whether the result of process to be applied to the received packets exists or not by referring to the cache memory; an output interface for transmitting the packets; a means for processing a cache miss, that is generated if the result of process conducted for the received packets does not exist in the cache memory, when the cache miss is generated; and a network processor interface for connection to a network processor, wherein the means for processing cache miss comprising;
integrated processors for transferring the cache miss; and
an interface for referring to a routing table required by the integrated processors for the transfer process. - View Dependent Claims (18, 19, 20, 21)
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22. A network-processor accelerator, comprising:
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an interface unit for temporarily storing the received packets; a packet analysis unit for obtaining the extracted information by extracting the necessary domain from the received packets; a cache memory for storing the process result required for transfer process of the received packets; an address generation means for referring to the cache memory from the extracted information; a means for determining whether the relevant information exists or not in the cache memory as the result of reference to the cache memory from the extracted information; a means for reassembling the packets from the relevant information when the relevant information exists in the cache memory; a primary table for management of the packets as cache miss packets when the relevant information does not exist in the cache memory; a secondary table for management of the second and subsequent packets that are containing the relevant information not existing in the cache memory and are expected to provide the process result which is identical to that of the packets recorded in the primary table; an interface unit for transmitting the packets and necessary information to an external connected network processor for implementing, with a programmable manner, the processes of cache miss packet recorded to the primary table; an interface unit for receiving the processed packets and added information from the external connected network processor; a means for recording the process result information of the processed packets to the cache memory; a means for applying the process result to the relevant packets recorded to the secondary table; a means for releasing the entries of the primary and secondary tables having completed the processes; a means for generating the transmitting packets from the processed packets or the process result information; and an interface unit for transmitting the processed packets. - View Dependent Claims (23, 24, 25)
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Specification
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Current AssigneeHitachi, Ltd.
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Original AssigneeHitachi, Ltd.
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InventorsOkuno, Michitaka
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Primary Examiner(s)Orgad; Edan
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Assistant Examiner(s)PARK, JUNG H
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Application NumberUS10/956,089Publication NumberTime in Patent Office1,478 DaysField of SearchNoneUS Class Current370/392CPC Class CodesH04L 45/00 Routing or path finding of ...H04L 45/60 Router architecturesH04L 49/3009 Header conversion, routing ...
