Boost DC-DC converter and semiconductor device having boost DC-DC converter

• US 7,443,152 B2
• Filed: 04/26/2006
• Issued: 10/28/2008
• Est. Priority Date: 04/28/2005
• Status: Active Grant

• Current Assignee: Ablic Inc. (MinebeaMitsumi Inc.)
• Original Assignee: Seiko Instruments Incorporated (Seiko Group)
• Inventors: Utsunomiya, Fumiyasu
• Primary Examiner(s): Han; Jessica
• Assistant Examiner(s): PHAM, EMILY P
• Application Number:
  US11/412,311
• Publication Number:
  US 20060256591A1
• Time in Patent Office: 916 Days
• Field of Search: 323/222, 323/259, 323/282, 323284-286
• US Class Current: 323/284
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/156 with automatic control of output voltage or current, e.g. switching regulators

Abstract

Provided is a boost DC-DC converter where electric power to be supplied to a booster circuit is supplied from a power supply and from boosted electric power of the booster circuit which can be actuated at a low voltage. The boost DC-DC converter has a structure in which: a switching device is provided between the power supply and a boosted output of the booster circuit; a storage capacitor for storing electric power to be inputted to the booster circuit and for operating the booster circuit for a predetermined length of time using the stored electric power is additionally provided; and in a case where the booster circuit can generate boosted electric power even when the switching device is turned off, the switching device is turned off.

Claims

1. A semiconductor device, comprising:

an input power supply configured to supply input power;

a booster circuit configured to boost the input power supplied from the input power supply, the booster circuit having an input terminal that receives the input power from the input power supply, a power receiving terminal that receives operation power for operating the booster circuit, and an output terminal that outputs the boosted input power to a load;

a switching device connected between the input power supply and the power receiving terminal of the booster circuit and configured to switch the operation power received by the power receiving terminal between the input power from the input power supply and the boosted input power from the output terminal; and

a voltage detection circuit responsive to a voltage change of the operation power at the power receiving terminal of the booster circuit to control the switching device to select between the input power from the input power supply and the boosted input power from the output terminal.

2. A semiconductor device according to claim 1, wherein the voltage detection circuit is configured to detect:

a second threshold voltage that is higher than a lowest operational voltage of the booster circuit; and

a first threshold voltage that is lower than the second threshold voltage.

3. A semiconductor device according to claim 2, wherein the voltage detection circuit is configured to:

switch the switching device to select the boosted input power from the output terminal when the voltage detection circuit detects that a voltage at the power receiving terminal becomes equal to or higher than the second threshold voltage; and

hold the switching device to keep the boosted input power selected until the voltage detection circuit detects that the voltage at the power receiving terminal becomes equal to or lower than the first threshold voltage.

4. A semiconductor device according to claim 2, wherein the voltage detection circuit is configured to:

switch the switching device to select the input power from the input power supply when the voltage detection circuit detects that a voltage at the power receiving terminal becomes equal to or lower than the first threshold voltage; and

hold the switching device to keep the input power selected until the voltage detection circuit detects that the voltage at the power receiving terminal becomes equal to or higher than the second threshold voltage.

5. A semiconductor device according to claim 2, wherein the first threshold voltage is lower than the lowest operational voltage of the booster circuit.

11. A semiconductor device according to claim 1, wherein the switching device comprises a MOS transistor whose drain is connected to the input power supply, the gate is connected to the voltage detection circuit and the source is connected to both the power receiving terminal and the output terminal of the booster circuit, and

the MOS transistor is turned on and off by the voltage detection circuit so that the MOS transistor is turned on to electrically connect the input power supply to the power receiving terminal of the booster circuit so as to supply the input power to the power receiving terminal, wherein being turned off to electrically isolate the input power supply from the power receiving terminal so as to supply the boosted input power to the power receiving terminal.

12. A semiconductor device according to claim 11, further comprising a storage capacitor connected between the power receiving terminal of the booster circuit and a ground (GND), wherein the storage capacitor supplies the operation power to the power receiving terminal for a period of time after the MOS transistor is turned off.

6. A semiconductor device, comprising:

an input power supply configured to supply input power;

a booster circuit configured to boost the input power from the input power supply, the booster circuit having an input terminal that receives the input power form the input power supply, a power receiving terminal that receives operation power for operating the booster circuit, an output terminal that outputs a boosted input power to a load, and a clock output terminal that outputs a clock signal at a frequency variable according to an operation condition of the booster circuit;

a switching device connected between the input power supply and the power receiving terminal of the booster circuit and configured to switch the operation power received by the power receiving terminal between the input power from the input power supply and the boosted input power from the output terminal; and

a clock detection circuit responsive to a frequency change of the clock signal from the clock output terminal to control the switching device to select between the input power from the input power supply and the boosted input power from the output terminal.

7. A semiconductor device according to claim 6, wherein the clock detection circuit is configured to detect:

a second threshold frequency that is higher than a lowest frequency at which the booster circuit is operational to generate the boosted input power; and

a first threshold frequency that is lower than the second threshold frequency.

8. A semiconductor device according to claim 7, wherein the clock detection circuit is configured to:

switch the switching device to select the boosted input power from the output terminal when the clock detection circuit detects that the frequency of the clock signal becomes equal to or higher than the second threshold frequency; and

holding the switching device to keep the boosted input power selected until the clock detection circuit detects the frequency of the clock signal becomes equal to or lower than the first threshold frequency.

9. A semiconductor device according to claim 7, wherein the clock detection circuit is configured to:

switch the switching device to select the input power from the input power supply when the clock detection circuit detects that the frequency of the clock signal becomes equal to or lower than the first threshold frequency; and

holding the switching device to keep the input power selected until the clock detection circuit detects that the frequency of the clock signal becomes equal to or higher than the second threshold frequency is detected.

10. A semiconductor device according to claim 7, wherein the first threshold frequency is lower than the lowest frequency at which the booster circuit is operational to generate the boosted input power.

13. A semiconductor device according to claim 6, wherein the switching device comprises a MOS transistor whose drain is connected to the input power supply, the gate is connected to the voltage detection circuit and the source is connected to both the power receiving terminal and the output terminal of the booster circuit, and

the MOS transistor is turned on and off by the voltage detection circuit so that the MOS transistor is turned on to electrically connect the input power supply to the power receiving terminal of the booster circuit so as to supply the input power to the power receiving terminal, wherein being turned off to electrically isolate the input power supply from the power receiving terminal so as to supply the boosted input power to the power receiving terminal.

14. A semiconductor device according to claim 13, further comprising a storage capacitor connected between the power receiving terminal of the booster circuit and a ground (GND), wherein the storage capacitor supplies the operation power to the power receiving terminal for a period of time after the MOS transistor is turned off.