Signal detector

• US 7,443,927 B2
• Filed: 06/12/2007
• Issued: 10/28/2008
• Est. Priority Date: 03/15/2004
• Status: Expired due to Term

• Current Assignee: Ranging Optics LLC (IPValuation Partners, LLC)
• Original Assignee: Asia Optical Company Incorporated
• Inventors: Chang, Yi-Yang
• Primary Examiner(s): Bocure, Tesfaldet
• Application Number:
  US11/761,439
• Publication Number:
  US 20070230629A1
• Time in Patent Office: 504 Days
• Field of Search: 375/316, 375/340, 375/257, 375/377
• US Class Current: 375/316
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/065 Binary decisions

Abstract

A signal detector comprises a signal translator, a data signal detector, a clock signal detector and an inputting control circuit for detecting abnormal clock and data signals. The signal translator respectively converts differential data signals and differential clock signal into a single data signal and a single clock signal. The data signal detector outputs a data detecting signal according to the single data signal. The clock signal detector outputs a clock detecting signal according to the single clock signal. The interrupting control circuit receives the data detecting signal and outputs a shutdown signal when the single data signal is at high voltage level over a predefined ratio. The interrupting control circuit also receives the clock detecting signal and outputs the shutdown signal when the single clock signal abnormally disappears.

Claims

1. A signal detector, comprising

a signal translator converting differential data signals into a single data signal;

a data signal detector outputting a data detecting signal according to the single data signal; and

an interrupting control circuit receiving the data detecting signal and outputting a shutdown signal when the single data signal is at high voltage level over a predefined ratio.

2. The signal detector as claimed in claim 1, wherein the data signal detector comprising:

an integrating circuit coupled to the signal translator and converting the single data signal into an integrating signal, wherein when the single data signal is at high voltage level over the predefined ratio, the integrating signal is higher than a threshold voltage; and

a first inverter coupled to the integrating circuit and inverting the integrating signal to output the data detecting signal.

3. The signal detector as claimed in claim 2, wherein the integrating circuit comprises:

a first resistor coupled between the signal translator and a first node;

a second resistor coupled between the first node and ground; and

a capacitor coupled between the first node and ground.

4. The signal detector as claimed in claim 3, wherein the integrating circuit comprises an initial voltage at the first node and the initial voltage is a half of the threshold voltage.

5. The signal detector as claimed in claim 1, wherein the signal translator further converts differential clock signals into a single clock signal.

6. The signal detector as claimed in claim 5, further comprising:

a clock signal detector outputting a clock detecting signal according to the single clock signal;

wherein the interrupting control circuit receives the clock detecting signal and outputs the shutdown signal when the single clock signal abnormally disappears.

7. The signal detector as claimed in claim 6, wherein the clock signal detector comprises:

a rectification filter circuit coupled to the signal translator, converting the single clock signal into a DC signal; and

a second inverter coupled to the rectification filter circuit and inverting the DC signal into the clock detecting signal.

8. The signal detector as claimed in claim 7, wherein the rectification filter circuit is a micro inductor to receive the single clock signal to output the clock detecting signal.

9. The signal detector as claimed in claim 1, wherein the interrupting control circuit comprises:

a NPN BJT transistor comprising a base receiving the clock detecting signal, a collector coupled to ground and a emitter;

a PMOS transistor comprising a gate coupled to the emitter of the NPN BJT transistor and a first inverter, a source coupled to a first DC voltage and a drain outputting the shutdown signal according to data detecting signal and the clock detecting signal.

10. The signal detector as claimed in claim 1, wherein the signal translator is a LVPECL to LVTTL translator.

11. A signal detector, comprising

a signal translator respectively converting differential data signals and differential clock signal into a single data signal and a single clock signal;

a data signal detector outputting a data detecting signal according to the single data signal;

a clock signal detector outputting a clock detecting signal according to the single clock signal;

an interrupting control circuit receiving the data detecting signal and outputting a shutdown signal when the single data signal is at high voltage level over a predefined ratio and receiving the clock detecting signal and outputting the shutdown signal when the single clock signal abnormally disappears.

12. The signal detector as claimed in claim 11, wherein the data signal detector comprising:

an integrating circuit coupled to the signal translator and converting the single data signal into an integrating signal, wherein when the single data signal is at high voltage level over the predefined ratio, the integrating signal is higher than a threshold voltage; and

a first inverter coupled to the integrating circuit and inverting the integrating signal to output the data detecting signal.

13. The signal detector as claimed in claim 12, wherein the integrating circuit comprises:

a first resistor coupled between the signal translator and a first node;

a second resistor coupled between the first node and ground; and

a capacitor coupled between the first node and ground.

14. The signal detector as claimed in claim 11, wherein the clock signal detector comprises:

a rectification filter circuit coupled to the signal translator, converting the single clock signal into a DC signal; and

a second inverter coupled to the rectification filter circuit and inverting the DC signal into the clock detecting signal.

15. The signal detector as claimed in claim 14, wherein the rectification filter circuit is a micro inductor to receive the single clock signal to output the clock detecting signal.

16. The signal detector as claimed in claim 11, wherein the interrupting control circuit comprises:

a NPN BJT transistor comprising a base receiving the clock detecting signal, a collector coupled to ground and a emitter;

a PMOS transistor comprising a gate coupled to the emitter of the NPN BJT transistor and a first inverter, a source coupled to a first DC voltage and a drain outputting the shutdown signal according to the data detecting signal and the clock detecting signal.

17. The signal detector as claimed in claim 11, wherein the signal translator is a LVPECL to LVTTL translator.