Computer-readable recording medium storing semiconductor designing program for improving both integration and connection of via-contact and metal

• US 7,444,614 B2
• Filed: 10/21/2004
• Issued: 10/28/2008
• Est. Priority Date: 09/10/1999
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Maeno, Muneaki, Sei, Toshikazu, Kimura, Kenji
• Primary Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US10/968,925
• Publication Number:
  US 20060012050A1
• Time in Patent Office: 1,468 Days
• Field of Search: 716/4, 716/6, 716 8- 14, 716/19, 716/21, 365/72, 257773-776, 257/758, 257/734, 257/369
• US Class Current: 716/50
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device has a via-contact, a main wire having an end connected to the via-contact, and an extension extended in line with the main wire from the end of the main wire beyond the via-contact, the width of the extension being equal to or narrower than the width of the main wire. The extension prevents the end of the main wire from being rounded by an optical proximity effect, eliminates a contact defect or an open defect between the via-contact and the end of the main wire, and involves no widening of the main wire around the via-contact, so that other via-contacts may be arranged in the vicinity of the via-contact in question without violating design rules.

Claims

1. A computer-readable recording medium for storing a program for driving a computer to generate a set of mask patterns, the mask patterns being used to manufacture a semiconductor device having X (X being a natural number) wiring layers, wherein the program includes the steps of:

arranging functional blocks and elements of the semiconductor device in a chip area scheduled for manufacturing the semiconductor device with the use of an automatic layout tool;

arranging main wires in a layer N of the semiconductor device (N satisfying 0<

=N<

=X−

1), main wires in a layer N+1 of the semiconductor device, and via-contacts in the layer N with the use of the automatic layout tool, to connect the functional blocks and elements to one another through the main wires and via-contacts; and

arranging extensions of the main wires that extend only in line with the main wires in the layer N and N+1, respectively, together with the via-contacts in the layer N, with the use of the automatic layout tool,

wherein a width of each extension is equal to or narrower than a width of its corresponding main wire.

2. The computer-readable recording medium of claim 1, wherein:

arranging each of the extensions formed in the layer N+1, that is in line with the corresponding main wire and is extended beyond the corresponding via-contact; and

arranging each of the extensions formed in the layer N, that is in line with the corresponding main wire and is extended beyond the corresponding via-contact.

3. The computer-readable recording medium of claim 1, wherein:

arranging each of the extensions formed in the layer N+1, that is orthogonal to the corresponding main wire and is extended beyond the corresponding via-contact; and

arranging each of the extensions formed in the layer N, that is orthogonal to the corresponding main wire and is extended beyond the corresponding via-contact.