Dynamic array architecture

CAFC
  • US 7,446,352 B2
  • Filed: 03/07/2007
  • Issued: 11/04/2008
  • Est. Priority Date: 03/09/2006
  • Status: Active Grant
First Claim
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1. A semiconductor device, comprising:

  • a substrate portion;

    a plurality of diffusion regions defined within the substrate portion, the plurality of diffusion regions separated from each other by a non-active region of the substrate portion;

    a plurality of linear gate electrode tracks defined to extend over the substrate portion and over some of the plurality of diffusion regions in a single common direction, at least one of the linear gate electrode tracks having multiple linear gate electrode segments adjacently defined thereover in an end-to-end manner such that facing ends of adjacent linear gate electrode segments are physically and electrically separated by a line end spacing of minimum size, wherein a size of each line end spacing within a window of lithographic influence is substantially the same, wherein the minimum size of the line end spacing corresponds to a substantially full occupancy of the at least one linear gate electrode track by the multiple linear gate electrode segments, wherein some of the linear gate electrode segments are defined to have different lengths to construct logic gate devices, wherein the length of each linear gate electrode segment is measured in a direction of its linear gate electrode track; and

    a plurality of interconnect layers defined above the plurality of linear gate electrode tracks, wherein at least one of the plurality of interconnect layers includes a plurality of linear conductor tracks defined to extend over the substrate portion in a single common direction within a given interconnect layer, each linear conductor track having one or more linear conductor segments defined thereover, wherein linear conductor segments defined in an adjacent end-to-end manner over a given linear conductor track have their facing ends physically and electrically separated by a conductor line end spacing of minimum size, wherein the minimum size of the conductor line end spacing corresponds to a maximum occupancy of the given linear conductor track by the linear conductor segments defined thereover.

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