Methods and system for improving integrated circuit layout

CAFC
  • US 7,448,012 B1
  • Filed: 04/15/2005
  • Issued: 11/04/2008
  • Est. Priority Date: 04/21/2004
  • Status: Active Grant
First Claim
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1. A method for generating design layout artwork implemented in a computer, comprising:

  • receiving a design layout comprising a plurality of layout objects residing on a plurality of layers;

    receiving descriptions of manufacturing process;

    constructing a system of initial constraints among said layout objects;

    computing local process modifications to change said initial constraints using said descriptions of manufacturing process;

    constructing new local constraint distances by combining said local process modifications with constraint distances in said system of initial constraints;

    enforcing said new local constraint distances; and

    updating the coordinate variables of layout objects according to the solutions obtained from enforcing said new local constraint distances;

    whereby a new layout is produced that has increased yield and performance.

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