Crossbar apparatus for a forwarding table memory in a router

• US 7,450,438 B1
• Filed: 04/17/2003
• Issued: 11/11/2008
• Est. Priority Date: 06/20/2002
• Status: Expired due to Fees

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Lynch, William L., Holst, John C.
• Primary Examiner(s): Nguyen; Van Thu
• Assistant Examiner(s): Sofocleous; Alexander
• Application Number:
  US10/418,634
• Time in Patent Office: 2,035 Days
• Field of Search: 365/230.01, 365/230.06, 365/189.07, 365/189.08, 365/189.17, 365/189.2, 712/10, 712/11, 712/14, 712/15, 712/16, 712/32, 712/33, 712/37, 370/381, 370/382, 370/383, 370/395.7, 370/395.71, 370/395.72
• US Class Current: 365/189.07
• CPC Class Codes: H04L 12/66 Arrangements for connecting between networks having differing types of switching systems, e.g. gateways
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/54 Organization of routing tables
• CPC Class Codes: H04L 45/60 Router architectures

Abstract

A router including a lookup execution unit including a plurality of stages, a forwarding table memory arranged in hierarchy including addressable sectors, blocks, and entries, and a crossbar having an address crossbar for selectively coupling one of the plurality of stages to a sector of the memory so that data from the sector can be read. In one example, any one of the stages of the plurality of stages may be selectively and dynamically coupled with any one of the sectors of the forwarding table memory for providing an address to a particular sector of the memory to read data therefrom.

Claims

1. A programmable crossbar for dynamically coupling a plurality of stages of an execution unit to one or more portions of a memory, comprising:

a set of address lines coupled with each stage of said plurality of stages for receiving an address signal from at least one stage; and

logic for selectively coupling one of said plurality of stages to a portion of the memory, said logic receiving said set of address lines from each stage, said logic comparing a portion of said address signal to one or more hardwired addresses associated with each portion of the memory, said logic receiving a plurality of programmable enable signals corresponding to each stage of said plurality of stages;

wherein when the portion of said address signal from one stage of said plurality of stages matches one of the hardwired addresses associated with one portion of the memory, then the one stage of said plurality of stages is coupled with the one portion of memory if the programmable enable signal associated with the one stage is active;

wherein the memory includes an on-chip memory and an off-chip memory, and wherein the plurality of stages of the execution unit and the on-chip memory are placed on a same chip.

2. The crossbar of claim 1, wherein the set of address lines includes a plurality of differential pairs of address lines, each differential pair representing a single address bit.

3. The crossbar of claim 2, wherein the plurality of differential pairs of address lines are interleaved along their length.

4. The crossbar of claim 1, wherein the logic further comprises:

a multiplexer for receiving the address signals from each of the stages and selecting the address signals associated with one stage of the stages based on a plurality of select lines;

a comparator for comparing a portion of the address signal from one stage of said plurality of stages to a hardwired addresses associated with one portion of the memory;

a logic gate receiving an output from the comparator and receiving a programmable enable signal associated with the one stage, said logic gate activating a select line associated with a stage based on the output from the comparator and a state of the programmable enable signal, thereby effecting the multiplexer to select the address signals of the one stage for connection with the memory.

5. The crossbar of claim 1, further comprising:

a set of data lines from the memory;

logic for dynamically coupling the set of data lines to one stage of the plurality of stages.

6. The crossbar of claim 5, wherein the data lines includes a plurality of differential pair data lines, each differential pair data line representing a single data bit.

7. The crossbar of claim 6, wherein the plurality of differential pair data lines are interleaved along their length.