Voltage regulator outputting positive and negative voltages with the same offsets

• US 7,453,312 B2
• Filed: 05/07/2008
• Issued: 11/18/2008
• Est. Priority Date: 04/28/2006
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Lin, Ching-Yuan, Lin, Yen-Tai
• Primary Examiner(s): Nguyen; Long
• Assistant Examiner(s): Jager; Ryan C
• Application Number:
  US12/116,229
• Publication Number:
  US 20080218252A1
• Time in Patent Office: 195 Days
• Field of Search: 327535-537, 363/59, 363/60
• US Class Current: 327/535
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: H02M 1/009 having two or more independently controlled outputs for DC-DC converter with intermediate AC H02M3/33561
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/071 adapted to generate a negative voltage output from a positive voltage source

Abstract

A voltage regulator has a first charge circuit, a second charge circuit, and a control circuit. The control circuit has five input terminals and two output terminals. The five input terminals are respectively coupled to a reference voltage, a first voltage source, a second voltage source, an output terminal of the first charge circuit, and an output terminal of the second charge circuit. The control circuit equalizes a voltage difference between the output terminal of the first charge circuit and the first voltage source and a voltage difference between the second voltage source and the output terminal of the second charge circuit.

Claims

1. A voltage regulator coupled to a first voltage source and a second voltage source, the voltage regulator comprising:

a first pump circuit coupled to the first voltage source;

a second pump circuit coupled to the second voltage source; and

a control circuit comprising;

a first resistor having a first end coupled to an output terminal of the first pump circuit;

a second resistor having a first end coupled to a second end of the first resistor and a second end coupled to an output terminal of the second pump;

a first transistor having a first terminal coupled to the output terminal of the first pump circuit and a second end coupled to the second end of the first resistor;

a second transistor having a first end coupled to a third terminal of the first transistor, a second end and a third end both coupled to the second voltage source;

a first voltage comparison circuit having a first input terminal coupled to a reference voltage and a second input terminal coupled to the third terminal of the first transistor;

a first voltage divider coupled to the output terminal of the first pump circuit and the output terminal of the second pump;

a second voltage divider coupled to the first voltage source and the second voltage source; and

a second voltage comparison circuit having a first input terminal coupled to the output terminal of the first voltage divider, a second input terminal coupled to the output terminal of the second voltage divider, and a third input terminal coupled to an output terminal of the first voltage comparison circuit, the second voltage comparison circuit being used for controlling operations of the first pump circuit and the second pump circuit according to the voltage levels of the three input terminals of the second voltage comparison circuit.

2. The voltage regulator of claim 1 wherein the second voltage comparison circuit comprises:

a comparator coupled to the output terminal of the first voltage divider and the output terminal of the second voltage divider for comparing the voltage level of the output terminal of the first voltage divider with the voltage level of the output terminal of the second voltage divider;

an inverter coupled to an output terminal of the comparator;

an AND gate having two input terminals respectively coupled to the output terminal of the first voltage comparison circuit and an output terminal of the comparator for executing an AND operation according voltage levels of the output terminals of the first voltage comparison circuit and the comparator; and

a second AND gate having two input terminals respectively coupled to the output terminal of the first voltage comparison circuit and an output terminal of the inverter for executing an AND operation according voltage levels of the output terminals of the first voltage comparison circuit and the inverter.

3. The voltage regulator of claim 2 wherein the first voltage comparison circuit and the comparator are operational amplifiers.

4. The voltage regulator of claim 2 wherein an output terminal of the first AND gate is coupled to the first pump circuit, and an output terminal of the second AND gate is coupled to the second pump circuit.

5. The voltage regulator of claim 2 wherein an output terminal of the first AND gate is coupled to the second pump circuit, and an output terminal of the second AND gate is coupled to the first pump circuit.

6. The voltage regulator of claim 1 wherein the first transistor and the second transistor have the same electrical characteristics.

7. The voltage regulator of claim 1 wherein the first voltage divider comprises two series connected resistors with the same resistance coupled to the output terminal of the first voltage divider.

8. The voltage regulator of claim 1 wherein the second voltage divider comprises two series connected resistors with the same resistance coupled to the output terminal of the second voltage divider.

9. The voltage regulator of claim 1 wherein the resistance of the first resistor is less than the resistance of the second resistor.

10. The voltage regulator of claim 1 wherein the first voltage comparison circuit is an operational amplifier.

11. The voltage regulator of claim 1 wherein the first transistor and the second transistor are P-type metal-oxide semiconductor (PMOS) transistors, and the first terminal, the second terminal, and the third terminal of each of the transistors are respectively a source, a gate, and a drain of the PMOS transistor.