Photoelectric conversion element having a plurality of semiconductor regions and including conductive layers provided on each isolation element region
First Claim
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1. An image pickup apparatus comprising:
- a plurality of a photoelectric conversion element having a first semiconductor region of a first conductive type, a plurality of second semiconductor regions of a second conductive type forming a junction with the first semiconductor region, a third semiconductor region of a first conductive type, provided in the first semiconductor region between mutually adjacent second semiconductor regions;
an element isolation region respectively provided between the third semiconductor region and each of the mutually adjacent second semiconductor regions; and
a conductive layer provided on each element isolation region.
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Abstract
To provide a solid-state image pickup apparatus with little or no difference in the dark currents between adjacent photoelectroc conversion elements and providing a high sensitivity and a low dark current even in-a high-speed readout operation.
A well is formed on a wafer, and diffusion layers are formed in the well to constitute a photodiode. A well contact is formed between the diffusion layers. Element isolation regions are provided between the well contact and the diffusion layers, and conductive layers are provided respectively on the element isolation regions, thereby reducing a difference in the minority carrier diffusions from the well contact to the photodiodes (diffusion layers).
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9 Claims
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1. An image pickup apparatus comprising:
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a plurality of a photoelectric conversion element having a first semiconductor region of a first conductive type, a plurality of second semiconductor regions of a second conductive type forming a junction with the first semiconductor region, a third semiconductor region of a first conductive type, provided in the first semiconductor region between mutually adjacent second semiconductor regions; an element isolation region respectively provided between the third semiconductor region and each of the mutually adjacent second semiconductor regions; and a conductive layer provided on each element isolation region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification