Method and circuit for determining the response curve knee point in active pixel image sensors with extended dynamic range
First Claim
1. An image array pixel comprising:
- a charge sharing node;
a photosensor coupled to said charge storing node;
a controllable voltage source for supplying one of a first and second voltage level;
said first voltage level being higher than said second voltage level;
a reset transistor having source/drain regions on opposite sides of a gate, one of said source/drain regions being switchably coupled to an output of said controllable voltage source first and second voltage sources for providing first and second voltages, respectively, the other of said source/drain regions being coupled to said charge storing node;
a reset control circuit coupled to a gate of said reset transistor, said reset control circuit for selectively providing a first reset control signal at a first level and a second reset control signal at a second level, said first level being higher than said second level,said reset control circuit and controllable voltage source being controllable during first, second, and third time intervals such that;
during said second time interval, said reset control circuit supplies said second reset control signal to said gate of said reset transistor while said controllable voltage source provides said second voltage to operate said reset transistor to partially remove charges from said photosensor,during said third time interval, said reset control circuit supplies said first reset control signal to said gate of said reset transistor, said controllable voltage source provides said first voltage to substantially remove all charges from said photosensor.
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Accused Products
Abstract
An apparatus and method for measuring the breakpoint of a response curve representing the voltage output of an image array having an extended dynamic range. By flooding a light-opaque pixel with a charge and then applying an intermediate reset voltage to the pixel, the signal is read from the pixel and stored. The full reset voltage is applied to the pixel, and then the signal in the pixel is read and stored. The voltage output difference is the difference between the first and second stored signal. The voltage output difference is then used to determine the voltage of the knee point. Further, a conventional saturated pixel can be reset with an intermediate reset just prior to readout. The resulting signal can then be used to determine the voltage of the knee point.
16 Citations
25 Claims
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1. An image array pixel comprising:
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a charge sharing node; a photosensor coupled to said charge storing node; a controllable voltage source for supplying one of a first and second voltage level;
said first voltage level being higher than said second voltage level;a reset transistor having source/drain regions on opposite sides of a gate, one of said source/drain regions being switchably coupled to an output of said controllable voltage source first and second voltage sources for providing first and second voltages, respectively, the other of said source/drain regions being coupled to said charge storing node; a reset control circuit coupled to a gate of said reset transistor, said reset control circuit for selectively providing a first reset control signal at a first level and a second reset control signal at a second level, said first level being higher than said second level, said reset control circuit and controllable voltage source being controllable during first, second, and third time intervals such that; during said second time interval, said reset control circuit supplies said second reset control signal to said gate of said reset transistor while said controllable voltage source provides said second voltage to operate said reset transistor to partially remove charges from said photosensor, during said third time interval, said reset control circuit supplies said first reset control signal to said gate of said reset transistor, said controllable voltage source provides said first voltage to substantially remove all charges from said photosensor. - View Dependent Claims (2, 3, 4, 5)
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6. An imaging device, comprising:
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a processor; an imager array coupled to said processor, one pixel of said image array comprising; a charge sharing node; a reset control circuit configured to provide a plurality of non-zero voltages; a row select transistor being switchably coupled to a first and second voltage, a gate of said row select transistor being coupled to a row select control line; and a reset transistor having source/drain regions on opposite sides of a gate, one of said source/drain regions being switchably coupled to said first and second voltage, the other of said source/drain regions being coupled to said node, a gate of reset transistor being coupled to said reset control circuit. - View Dependent Claims (7, 8, 9)
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10. An imager circuit comprising:
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a controllable voltage source for selectively supplying one of a first lower voltage level and a second higher voltage level to a voltage supply line; a pixel comprising; a charge storage node; a photosensor coupled to said storage node; a reset transistor coupled between said voltage supply line and said storage node, said reset transistor having a gate input; and a control circuit for providing control signals to said controlable voltage source and gate of said reset transistor, said control circuit configured such that; during a first time period, said reset transistor is supplied with a gate control signal at a first level while said controllable voltage source supplies said second higher voltage level to said voltage supply line, during a second time period, said reset transistor is supplied with a gate control signal at a second level lower than said first level but above a threshold voltage of said reset transistor while said controllable voltage source supplies said second higher voltage level to said voltage supply line. - View Dependent Claims (11, 12, 13)
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14. A pixel array comprising:
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at least one pixel circuit comprising; a storage node for storing charges; a reset transistor for controlling the charges stored at said storage node; a circuit for operating said reset transistor to fill the storage node with electrons, to partially remove electrons from said storage node, and to substantially remove all charges from said storage node; and a readout circuit for providing a first signal representing charges at said storage node after electrons are partially removed from said storage node and a second signal representing charges at said storage node after all charges are removed from said storage node. - View Dependent Claims (15, 16, 17, 18)
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19. A pixel comprising:
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a first voltage source having an output switchable between a first and second reset supply voltage in response to a first control signal; a charge storage region; a reset transistor connected between said first voltage source and said charge storage region; and a control circuit for providing a gate control voltage to a gate of said reset transistor, said control circuit selectively providing a first operating control voltage and a second operating control voltage to said reset transistor, said second operating control voltage being less than said first operating control voltage and higher than a zero voltage. - View Dependent Claims (20, 21)
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22. An image array pixel comprising:
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a charge storing node; a photosensor coupled to said charge storing node; a voltage source; a reset transistor having source/drain regions on opposite sides of a gate, one of said source/drain regions being coupled to an output of said voltage source the other of said source/drain regions being coupled to said charge storing node; a sample and hold circuit having first and second storage areas selectively coupled to said charge storing node; and a control circuit for operating said reset transistor and said sample and hold circuit for providing a correlated double sampling and holding of a charge integrated signal and a full reset signal during a one sample and hold period and for providing a sampling and holding of a first full reset signal with said reset transistor receiving a first gate control signal and a second less than full reset signal with said reset transistor receiving a second gate control signal which is lower than said first gate control signal during a second sample and hold period. - View Dependent Claims (23, 24)
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25. An image array comprising:
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a controllable voltage source being selectively mutually exclusively coupled to a first voltage source and a second voltage source for supplying a first and a second voltage level, respectively, said first voltage level being different from said second voltage level; a pixel comprising; a reset transistor having source/drain regions on opposite sides of a gate, one of said source/drain regions being switchably coupled to an output of said controllable voltage source, the other of said source/drain regions being coupled to an associated charge storing node; and a reset control circuit coupled to a gate of said reset transistor, said reset control circuit configured to provide a first reset control signal at a first level, a second reset control signal at a second level, and a third reset control signal at a third level;
where said first level is different from said second and third levels, where said second level is different from said third level.
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Specification