Dielectric relaxation memory

• US 7,457,184 B2
• Filed: 03/27/2006
• Issued: 11/25/2008
• Est. Priority Date: 09/01/2004
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sandhu, Gurtej, Basceri, Cem
• Primary Examiner(s): Pham; Ly D
• Application Number:
  US11/389,150
• Publication Number:
  US 20060163633A1
• Time in Patent Office: 974 Days
• Field of Search: 365/149, 365/222, 257/302, 257/330
• US Class Current: 365/222
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto

Abstract

A capacitor structure having a dielectric layer disposed between two conductive electrodes, wherein the dielectric layer contains at least one charge trap site corresponding to a specific energy state. The energy states may be used to distinguish memory states for the capacitor structure, allowing the invention to be used as a memory device. A method of forming the trap cites involves an atomic layer deposition of a material at pre-determined areas in the dielectric layer.

Claims

1. A method of operating a memory device comprising the acts of:

applying a first voltage to an electrode of a capacitor structure;

reading out a current from the capacitor structure;

applying a second voltage to an electrode of a capacitor structure, wherein the second voltage is greater than the first voltage such that the second voltage causes charge trap sites located within a dielectric layer of the capacitor structure to fill with charge; and

reading out a second current from the capacitor structure.

2. The method of claim 1, further comprising the act of reapplying the second voltage.

3. The method of claim 1, wherein the act of reapplying the second voltage is performed at pre-determined intervals of time.

4. The method of claim 1, wherein the second voltage is pulsed.

5. The method of claim 4, wherein the second voltage is pulsed, such that the applied voltage returns to the first applied voltage.

6. The method of claim 1, wherein the step of reading out a first and second current comprises reading out a current from the capacitor on an associated bit line.

7. The method of claim 6, further comprising the step of comparing the first current to the second current to determine a memory state of the memory device.

8. A method of operating a memory device comprising the acts of:

applying a first voltage to a capacitor structure, wherein the first voltage writes a first memory state;

reading put a first current from the capacitor structure when representing the first memory state;

applying a second voltage to the capacitor structure, wherein the second voltage causes charge trap sites located within a dielectric layer of the capacitor structure to fill with charge and writes a second memory state; and

reading out a second current from the capacitor structure when representing the second memory state.

9. The method of claim 8, further comprising the step of comparing the first current to the second current.

10. The method of claim 8, further comprising the step of refreshing the second memory state of the capacitor by reapplying the second voltage.

11. The method of claim 10, wherein the step of reapplying the second voltage is done at pre-determined time intervals.