Insulated gate semiconductor device with small feedback capacitance and manufacturing method thereof

• US 7,459,751 B2
• Filed: 09/01/2005
• Issued: 12/02/2008
• Est. Priority Date: 09/07/2004
• Status: Expired due to Fees

• Current Assignee: North Plate Semiconductor, LLC
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sugiyama, Koichi
• Primary Examiner(s): Sefer, A.
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US11/216,014
• Publication Number:
  US 20060049456A1
• Time in Patent Office: 1,188 Days
• Field of Search: 257/213, 257/288, 257/327, 257/335, 257/340, 257/E29.006, 257/E29.007, 257/E29.008, 257/E29.009, 257/E29.01, 257/E29.011, 438/133, 438/140, 438/142, 438/147, 438/149, 438/200, 438/202, 438/257, 438/284, 438/400, 438/454
• US Class Current: 257/340
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

Disclosed is an insulated gate semiconductor device including a first region having a gate electrode region and a first insulating film region surrounding the gate electrode region; a semiconductor region which includes a channel forming region and is disposed to oppose the gate electrode region with the first insulating film region between them; and a second region which has a conductor region buried in a semiconductor region not including the channel forming region disposed to oppose the gate electrode region with the first insulating film region between them, and has a second insulating film region which separates the conductor region from the semiconductor region.

Claims

1. An insulated gate semiconductor device, comprising:

a first region having a gate electrode region and a first insulating film region surrounding the gate electrode region;

a semiconductor region including a channel forming region and provided to oppose the gate electrode region with the first insulating film region between the semiconductor region and the gate electrode region; and

a second region buried in the semiconductor region so as to reach a vertical position deeper than the first region and being adjacent to and in contact with the first region, the second region having a conductor region and a second insulating film region to separate the conductor region from the semiconductor region,

wherein the first region is buried in first groove-like removed portions of the semiconductor region; and

wherein the second region is buried in second groove-like removed portions of the semiconductor region, and provided to oppose at least the channel forming region of the semiconductor region through the first region.

2. The insulated gate semiconductor device as set forth in claim 1, wherein the second groove-like removed portions of the semiconductor region for the second region have a depth larger than that of the first groove-like removed portions of the semiconductor region for the first region.

3. An insulated gate semiconductor device, comprising:

a first region having a gate electrode region and a first insulating film region surrounding the gate electrode region;

a semiconductor region including a channel forming region and provided to oppose the gate electrode region with the first insulating film region between the semiconductor region and the gate electrode region; and

a second region buried in the semiconductor region so as to reach a vertical position deeper than the first region and being adjacent to and in contact with the first region, the second region having a conductor region and a second insulating film region to separate the conductor region from the semiconductor region,

wherein the second region is positioned between the first region and the semiconductor region so as to be in contact with the first region and the semiconductor region.

4. An insulated gate semiconductor device, comprising:

a first region having a gate electrode region and a first insulating film region surrounding the gate electrode region;

a semiconductor region including a channel forming region and an emitter region adjacent to the channel forming region, the semiconductor region being provided to oppose the gate electrode region with the first insulating film region between the semiconductor region and the gate electrode region; and

a second region buried in the semiconductor region so as to reach a vertical position deeper than the first region and being adjacent to and in contact with the first region, the second region having a conductor region and a second insulating film region to separate the conductor region from the semiconductor region, the second insulating film region being in contact with the semiconductor region, the conductor region being configured so as to have a same voltage as the emitter region,

wherein the insulated gate semiconductor device is an IGBT.

5. The insulated gate semiconductor device as set forth in claim 4, wherein the second region has the conductor region divided by the second insulating film region.

6. The insulated gate semiconductor device as set forth in claim 4, wherein a channel in the channel forming region is formed in a vertical direction.

7. The insulated gate semiconductor device as set forth in claim 4, wherein a channel in the channel forming region is formed in a lateral direction.

8. The insulated gate semiconductor device as set forth in claim 4, wherein the second insulating film region has a thickness larger than that of the first insulating film region.

9. The insulated gate semiconductor device as set forth in claim 4, wherein the second region is formed in plural discontinuously in a direction along the gate electrode region.

10. The insulated gate semiconductor device as set forth in claim 4, wherein the conductor region has a top surface used to be electrically conductive to the emitter region.

11. The insulated gate semiconductor device as set forth in claim 4, wherein the conductor region is formed of polycrystalline silicon.

12. The insulated gate semiconductor device as set forth in claim 4, wherein the second insulating film region of the second region is formed of silicon oxide.

13. The insulated gate semiconductor device as set forth in claim 4, wherein none of the semiconductor region is disposed between the first region and the second region.

14. The insulated gate semiconductor device as set forth in claim 4, wherein the first insulating film region has portions thereof each having a substantially same thickness and facing with each other through the gate electrode region.