Semiconductor component comprising flip chip contacts with polymer cores and method of producing the same

• US 7,462,940 B2
• Filed: 01/08/2007
• Issued: 12/09/2008
• Est. Priority Date: 01/11/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Mahler, Joachim, Haimerl, Alfred, Kessler, Angela, Schober, Wolfgang, Bauer, Michael
• Primary Examiner(s): Williams; Alexander O
• Application Number:
  US11/620,784
• Publication Number:
  US 20070182021A1
• Time in Patent Office: 701 Days
• Field of Search: 257/778, 257/E23.021, 257/E23.008, 257/E21.503, 257/E23.004, 257/E23.069, 257/E23.068, 257/734, 257/737, 257/738, 257/692, 257/700, 257/693, 257/701, 257/772, 257/779, 438/108
• US Class Current: 257/778
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13561 On the entire surface of the core, i.e. integral coating
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/92125 the second connecting process involving a layer connector
• CPC Class Codes: H01L 23/3192 Multilayer coating
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

A semiconductor component includes flip-chip contacts arranged on a wiring structure of a semiconductor chip. The wiring structure includes at least one metallization layer and at least one dielectric insulation layer made of a low-k material with a relative permittivity ε_r lower than the relative permittivity of a silicon dioxide. The flip-chip contacts are arranged on contact areas of an upper metallization layer and have a polymer core surrounded by a lead-free solder sheath.

Claims

1. A semiconductor component, comprising:

a semiconductor chip comprising a wiring structure including at least one metallization layer with contact areas and at least one dielectric insulation layer comprising a low-k material having a relative permittivity ε

_r that is lower than the relative permittivity of a silicon oxide; and

flip-chip contacts arranged on the contact areas of the metallization layer, the flip-chip contacts comprising a polymer core surrounded by a lead-free solder material.

2. The semiconductor component as claimed in claim 1, wherein the low-k material has a coefficient of thermal expansion that is lower than the coefficient of thermal expansion of silicon oxide.

3. The semiconductor component as claimed in claim 2, wherein the low-k material has a greater ductility than silicon oxide.

4. The semiconductor component as claimed in claim 1, wherein the low-k material includes a porous silicon dioxide.

5. The semiconductor component as claimed in claim 1, wherein the polymer core comprises a silicone.

6. The semiconductor component as claimed in claim 1, wherein the polymer core comprises a thermoplastic.

7. The semiconductor component as claimed in claim 1, wherein the polymer core comprises an elastomer.

8. The semiconductor component as claimed in claim 1, wherein the polymer core has a ball form.

9. The semiconductor component as claimed in claim 1, wherein the polymer core has a bump form.

10. The semiconductor component as claimed in claim 1, wherein the flip-chip contacts comprise internal connecting elements of the semiconductor component to a wiring substrate and are arranged and fixed on contact pads of a wiring structure on a top side of the wiring substrate.

11. The semiconductor component as claimed in claim 10, wherein an interspace between the semiconductor chip with flip-chip contacts and the top side of the wiring substrate is filled with an underfill material.

12. A method for producing a semiconductor component comprising flip-chip contacts, comprising:

producing a semiconductor chip including a wiring structure including at least one metallization layer with contact areas for the flip-chip contacts and at least one dielectric insulation layer comprising a low-k material having a relative permittivity ε

_r lower than the relative permittivity of a silicon oxide; and

applying the flip-chip contacts to the contact areas, the flip-chip contacts comprising a polymer core surrounded by a lead-free solder material.

13. The method as claimed in claim 12, wherein the semiconductor chip with the flip-chip contacts is arranged and fixed on contact pads of a wiring structure on a top side of a wiring substrate.

14. The method as claimed in claim 12, wherein an interspace between the semiconductor chip with flip-chip contacts and the top side of the wiring substrate is filled with an underfill material.

15. A semiconductor component, comprising:

a semiconductor chip comprising a wiring structure including at least one metallization layer with contact areas and at least one dielectric insulation layer comprising a low-k material having a relative permittivity ε

_r that is lower than the relative permittivity of a silicon oxide; and

flip-chip contacts arranged on the contact areas of the metallization layer, the flip-chip contacts comprising a polymer core entirely covered by a layer of a lead-free solder material.