Programming method for flash memory capable of compensating reduction of read margin between states due to high temperature stress

• US 7,463,526 B2
• Filed: 08/31/2006
• Issued: 12/09/2008
• Est. Priority Date: 01/12/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kang, Dong-Ku, Lim, Young-Ho
• Primary Examiner(s): Ho; Hoai V.
• Assistant Examiner(s): Lappas; Jason
• Application Number:
  US11/513,159
• Publication Number:
  US 20070159892A1
• Time in Patent Office: 831 Days
• Field of Search: 365/185.22
• US Class Current: 365/185.22
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2211/5621 Multilevel programming verification

Abstract

A programming method of a flash memory device having a plurality of memory cells for storing multi-bit data indicating one of a plurality of states. The programming method includes programming selected memory cells using multi-bit data to have one of the states; detecting programmed memory cells arranged within a predetermined region of threshold voltage distribution each corresponding to at least two of the states, wherein predetermined regions of the respective at least two states are selected by one of a first verify voltage and a read voltage and a second verify voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and simultaneously programming detected memory cells of the at least two states to have a threshold voltage being equivalent to or higher than the second verify voltage corresponding to each of the states.

Claims

1. A programming method for a flash memory device having a plurality of memory cells storing multi-bit data indicating one of a plurality of states, the programming method comprising:

programming selected memory cells with multi-bit data to have one of the plurality of states using a first programming operation;

following programming of the selected memory cells with multi-bit data using the first programming operation, detecting programmed memory cells arranged within a predetermined region of a threshold voltage distribution, the region corresponding to at least two of the plurality of states, wherein predetermined regions of the respective at least two of the plurality of states are selected by one of a first verify voltage and a read voltage and a second verify voltage, the first verify voltage being lower than the second verify voltage and higher than the read voltage; and

following detection of the programmed memory cells and using a second programming operation, simultaneously programming detected memory cells of the at least two of the plurality of states to have a threshold voltage equivalent to or higher than the second verify voltage corresponding to each of the plurality of states.

2. The programming method as recited in claim 1, wherein the plurality of states comprises a first state corresponding to an erased state for a memory cell and second, third and fourth states corresponding to different programmed states for a memory cell.

3. The programming method as recited in claim 1, wherein simultaneously programming the detected memory cells using the second programming operation comprises repeatedly applying a program voltage to a wordline associated with the detected memory cells in a programming loop that gradually increases with each iteration of the programming loop.

4. The programming method as recited in claim 1, wherein the first verify voltage is used to determine whether the selected memory cells are programmed with the multi-bit data.

5. A programming method for a flash memory device having a plurality of memory cells storing multi-bit data indicating one of at least four data states, the programming method comprising:

programming selected memory cells using multi-bit data to have one of second through fourth states using a first programming operation;

after programming of the selected memory cells using the first programming operation, detecting programmed memory cells, wherein detecting programmed memory cells comprises;

detecting programmed memory cells arranged within a predetermined region of a threshold voltage distribution corresponding to the second state, wherein the predetermined region of the second state is defined in relation to one of a first verify voltage and a first read voltage and a second verify voltage, the first verify voltage being lower than the second verify voltage and higher than the first read voltage;

detecting programmed memory cells arranged within a predetermined region of a threshold voltage distribution corresponding to the third state, wherein the predetermined region of the third state is defined in relation to one of a third verify voltage and a second read voltage and a fourth verify voltage, the third verify voltage being lower than the fourth verify voltage and higher than the second read voltage; and

after detecting programmed memory cells, simultaneously programming the detected memory cells of the second state and the detected memory cells of the third state to have a threshold voltage equivalent to or higher than the second and fourth verify voltages, respectively.

6. The programming method as recited in claim 5, wherein the at least four data states include an erase state associated with a lowest predetermined region of the threshold voltage distribution less than the respective predetermined regions of the threshold voltage distribution corresponding to the second and third states, and

simultaneously programming the detected memory cells of the second state and the detected memory cells of the third state comprises, applying a program voltage to a selected wordline, wherein the program voltage is used to program selected memory cells to the erase state during the first programming operation.

7. The programming method as recited in claim 6 wherein the program voltage increases gradually with repetition of a programming loop.

8. The programming method as recited in claim 6 wherein detecting programmed memory cells further comprises:

detecting programmed memory cells arranged within a predetermined region of a threshold voltage corresponding to the fourth state, wherein the predetermined region of the fourth state is defined in relation to one of a fifth verify voltage and a third read voltage and a sixth verify voltage, the fifth verify voltage being lower than the sixth verify voltage and higher than the third read voltage; and

simultaneously programming memory cells further comprises programming the detected memory cells of the fourth state to have a threshold voltage equivalent to or higher than the sixth verify voltage.

9. The programming method as recited in claim 5, wherein the first state indicates an erased state, and the second to fourth states indicate programmed states.

10. The programming method as recited in claim 8, wherein the first, third, and fifth verify voltages are used to determine whether the selected memory cells are programmed using multi-bit data.

11. A programming method for a flash memory device having a plurality of memory cells for storing multi-bit data indicating one of first through fourth data states, the programming method comprising:

programming selected memory cells using multi-bit data to have one of the second through fourth states using a first programming operation;

after programming of the selected memory cells using the first programming operation, detecting programmed memory cells, wherein detecting programmed memory cells comprises;

detecting programmed memory cells arranged within a predetermined region of a threshold voltage corresponding to the second state, wherein the predetermined region of the second state is selected by one of a first verify voltage and a first read voltage, and a second verify voltage, the first verify voltage being lower than the second verify voltage and higher than the first read voltage;

detecting programmed memory cells arranged within a predetermined region of a threshold voltage distribution corresponding to the third state, wherein the predetermined region of the third state is selected by one of a third verify voltage and a second read voltage, and a fourth verify voltage, the third verify voltage being lower than the fourth verify voltage and higher than the second read voltage;

detecting programmed memory cells arranged within a predetermined region of a threshold voltage corresponding to the fourth state, wherein the predetermined region of the fourth state is selected by one of a fifth verify voltage and a third read voltage, and a sixth verify voltage, the fifth verify voltage being lower than the sixth verify voltage and higher than the third read voltage; and

after detecting the programmed memory cells, simultaneously programming the detected memory cells of the second state, the detected memory cells of the third state, and the detected memory cells of the fourth state to respectively have a threshold voltage equivalent to or higher than the second, fourth, and sixth verify voltages.

12. The programming method as recited in claim 11 wherein when the detected memory cells are programmed simultaneously, a program voltage applied to a selected wordline is a lowest program voltage used to program the multi-bit data during the first programming operation.

13. The programming method as recited in claim 12, wherein the program voltage increases gradually with the repetition of a programming loop.

14. The programming method as recited in claim 11 wherein the first, third, and fifth verify voltages are used to determine whether the selected memory cells are programmed using multi-bit data.

15. A programming method for a flash memory device having a plurality of memory cells storing multi-bit data indicating an erased state or one of a plurality of programmed states, the programming method comprising:

programming selected memory cells with multi-bit data to have one of the plurality of programmed states;

detecting programmed memory cells arranged within a predetermined region of a threshold voltage distribution, the predetermined region corresponding to at least first and second states of the plurality of programmed states,

wherein a first portion of the predetermined region corresponding to the first state is defined in relation to a first verify voltage, a first read voltage and a second verify voltage, the first verify voltage being lower than the second verify voltage and higher than the first read voltage, and a second portion of the predetermined region corresponding to the second state is defined in relation to a third verify voltage, a second read voltage and a fourth verify voltage, the third verify voltage being lower than the fourth verify voltage and higher than the second read voltage; and

following detection of the programmed memory cells,

simultaneously programming the detected memory cells of first state to have a threshold voltage greater than or equal to the second verify voltage, and the detected memory cells of second state to have a threshold voltage greater than or equal to the fourth verify voltage.

16. The programming method as recited in claim 15 wherein detecting the programmed memory cells arranged within a predetermined region of a threshold voltage distribution comprises:

performing a first read operation on the programmed memory cells in relation to a first voltage ranging between either the first verify voltage and the second verify voltage, or between the first read voltage and the second verify voltage; and

performing a second read operation on the programmed memory cells in relation to a second voltage ranging between either the third verify voltage and the fourth verify voltage, or between the second read voltage and the fourth verify voltage.

17. The programming method as recited in claim 16 further comprising after the simultaneous programming of the detected memory cells:

performing a first verify operation by applying the second verify voltage to a selected word line associated with the detected memory cells; and

performing a second verify operation by applying the fourth verify voltage to the selected wordline.

18. The programming method as recited in claim 17 wherein simultaneously programming the detected memory cells comprises:

applying a program voltage to the selected wordline associated with the detected memory cells that is lower than any program voltage applied during the programming of the selected memory cells with the multi-bit data.

19. The programming method as recited in claim 18 further comprising:

upon determining from the first and second verify operations that the detected memory cells are not properly programmed, incrementing the program voltage applied to the selected wordline and again simultaneously programming the detected memory cells.