System for five-level non-causal channel equalization

• US 7,463,695 B2
• Filed: 07/17/2006
• Issued: 12/09/2008
• Est. Priority Date: 12/07/2001
• Status: Expired due to Term

• Current Assignee: Applied Micro Circuits Corporation (MACOM Technology Solutions Holdings, Inc.)
• Original Assignee: Applied Micro Circuits Corporation (MACOM Technology Solutions Holdings, Inc.)
• Inventors: Yuan, Warm Shaw, Conroy, Keith Michael, Castagnozzi, Daniel M.
• Primary Examiner(s): Tran; Khai
• Application Number:
  US11/487,732
• Publication Number:
  US 20060256891A1
• Time in Patent Office: 876 Days
• Field of Search: 375/287, 375/316, 375/317, 375/329, 714/708, 714/709, 714/754, 714/776, 341/68
• US Class Current: 375/287
• CPC Class Codes: H04L 1/0047 Decoding adapted to other signal detection operation in conjunction with sequence estimation or equalization H04L25/03286
• CPC Class Codes: H04L 2025/03356 Baseband transmission
• CPC Class Codes: H04L 25/061 providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset removal of dc offset in coupling arrangements H04L25/029, H04L25/0296
• CPC Class Codes: H04L 25/4906 using binary codes

Abstract

A system and method are provided for five-level non-causal channel equalization in a communications system. The method comprises: receiving a non-return to zero (NRZ) data stream input; establishing a five-level threshold; comparing the first bit estimate to a second bit value received prior to the first bit; comparing the first bit estimate to a third bit value received subsequent to the first bit; and, in response to the comparisons, determining the value of the first bit. Establishing a five-level threshold includes: establishing thresholds to distinguish a first bit value when the second and third bit values are a “1” value, when the second bit value is a “1” and the third bit value is a “0”, when the second bit value is a “0” and the third bit value is a “1”, when the second and third bit values are a “0” value, and an approximate midway threshold.

Claims

1. A five-level non-causal channel equalization communication system, the system comprising:

a multi-threshold decision circuit having an input to accept a non-return to zero (NRZ) data stream, an input to accept threshold values, and outputs to provide bit estimates responsive to five voltage threshold levels; and

,

a non-causal circuit having inputs to accept bit estimates from the multi-threshold decision circuit, the non-causal circuit comparing a current bit estimate to bit value decisions made across a plurality of clock cycles, the non-causal circuit having an output to supply a bit value for the current bit estimate determined in response to the non-causal bit value comparisons.

2. The system of claim 1 wherein the non-causal circuit includes:

a future decision circuit having inputs connected to the mutli-threshold circuit outputs, the future decision circuit having outputs to supply the current, first bit, estimate and a third bit value;

a present decision circuit having inputs to accept the first bit estimate, the third bit value, and a second bit value, the present decision circuit comparing the first bit estimate to both the second bit value, received prior to the first bit estimate, and the third bit value, received subsequent to the first bit estimate, the present decision circuit having an output to supply the first bit value determined in response to comparing the first bit estimates to the second and third bit values; and

,

a past decision circuit having an input to accept the first bit value and an output to supply the second bit value.

3. The system of claim 2 wherein the multi-threshold circuit includes:

a first comparator having an input to accept the NRZ data stream, an input establishing a first threshold (a11), and an output to supply a first bit estimate when the second and third bit values are equal to “

1”

;

a second comparator having an input to accept the NRZ data stream, an input establishing a second threshold (a10), and an output to supply a first bit estimate when the second bit value is a “

1” and

the third bit value is a “

0”

;

a third comparator having an input to accept the NRZ data stream, an input establishing a third threshold (Vopt), and an output to supply a signal having an approximately equal probability of being a “

0”

value as a “

1”

value;

a fourth comparator having an input to accept the NRZ data stream, an input establishing a fourth threshold (a01), and an output to supply a first bit estimate when the second bit value is a “

0” and

the third bit value is a “

1”

; and

,

a fifth comparator having an input to accept the NRZ data stream, an input establishing a fifth threshold (a00), and an output to supply a first bit estimate when the second and third bit values are equal to “

0”

.

4. The system of claim 3 wherein the multi-threshold circuit accepts an NRZ data stream encoded with forward error correction (FEC);

and,

the system further comprising;

a forward error correction (FEC) circuit having an input to receive the first bit value from the non-causal circuit, the FEC circuit decoding the incoming data stream and correcting bit values in response to the decoding, the FEC circuit having an output to supply threshold values to the multi-threshold circuit in response to the FEC corrections and an output to supply a stream of corrected data bits.

5. The system of claim 4 wherein the FEC circuit includes a first threshold generator having an inputs to accept the first bit values from the non-causal circuit and the stream of corrected data bits, the first threshold generator:

tracking the number of corrections in the first bit when the first bit is determined to be a “

0”

value and the second and third bits are both “

1”

values;

tracking the number of corrections in the first bit when the first bit is determined to be a “

1”

value and the second and third bits are both “

1”

values; and

,

wherein the first threshold generator has an output to supply the first threshold (a11) in response to the tracked corrections.

6. The system of claim 5 wherein the FEC circuit includes a fifth threshold generator having inputs to accept the first bit values from the non-causal circuit and the stream of corrected data bits, the fifth threshold generator:

tracking the number of corrections in the first bit when the first bit is determined to be a “

0”

value and the second and third bits are both “

0”

values;

tracking the number of corrections in the first bit when the first bit is determined to be a “

1”

value and the second and third bits are both “

0”

values; and

,

wherein the fifth threshold generator has an output to supply the fifth threshold (a00) in response to the tracked corrections.

7. The system of claim 6 wherein the FEC circuit includes a second threshold generator having inputs to accept the first bit values from the non-causal circuit and the stream of corrected data bits, the second threshold generator:

tracking the number of corrections in the first bit when the first bit is determined to be a “

0”

value, the second bit value is a “

1”

, and the third bits is a “

0”

value;

tracking the number of corrections in the first bit when the first bit is determined to be a “

1”

value, the second bit value is a “

1”

, and the third bits is a “

0”

value; and

,

wherein the second threshold generator has an output to supply the second threshold (a10) in response to the tracked corrections.

8. The system of claim 7 wherein the FEC circuit includes a fourth threshold generator having inputs to accept the first bit values from the non-causal circuit and the stream of corrected data bits, the fourth threshold generator:

tracking the number of corrections in the first bit when the first bit is determined to be a “

0”

value, the second bit value is a “

0”

, and the third bits is a “

1”

value;

tracking the number of corrections in the first bit when the first bit is determined to be a “

1”

value, the second bit value is a “

0”

, and the third bits is a “

1”

value; and

,

wherein the fourth threshold generator has an output to supply the fourth threshold (a01) in response to the tracked corrections.

9. The system of claim 8 wherein the FEC circuit includes a third threshold generator having inputs to accept the first bit values from the non-causal circuit and the stream of corrected data bits, the third threshold generator:

tracking the number of corrections in the first bit when the first bit is determined to be a “

0”

value;

tracking the number of corrections in the first bit when the first bit is determined to be a “

1”

value; and

,

wherein the third threshold generator has an output to supply the third threshold (Vopt) in response tracking the total number of “

0”

bit value and “

1”

bit value errors.

10. The system of claim 3 further comprising an averaging circuit, the averaging circuit including:

a first threshold generator having an input connected to the output of the non-causal circuit and an input to accept the NRZ data stream, the first threshold generator tracking the NRZ data stream inputs when the second and third bit values both equal “

1” and

maintaining a long-term average of the tracked NRZ data stream inputs, the first threshold generator having an output to supply the first threshold (a11) responsive to the long-term average.

11. The system of claim 10 wherein the averaging circuit further includes:

a fifth threshold generator having an input connected to the output of the non-causal circuit and an input to accept the NRZ data stream input, the fifth threshold generator tracking the NRZ data stream inputs when the second and third bit values both equal “

0” and

maintaining a long-term average of the NRZ data stream inputs, the fifth threshold generator having an output to supply the fifth threshold (a00) responsive to the long-term average.

12. The system of claim 11 wherein the averaging circuit further includes:

a second threshold generator having an input connected to the output of the non-causal circuit and an input to accept the NRZ data stream input, the second threshold generator tracking the NRZ data stream inputs when the second bit value is a “

1” and

the third bit value is a “

0” and

maintaining a long-term average of the NRZ data stream inputs, the second threshold generator having an output to supply the second threshold (a10) responsive to the long-term average.

13. The system of claim 12 wherein the averaging circuit further includes:

a fourth threshold generator having an input connected to the output of the non-causal circuit and an input to accept the NRZ data stream input, the fourth threshold generator tracking the NRZ data stream inputs when the second bit value is a “

0” and

the third bit value is a “

1” and

maintaining a long-term average of the NRZ data stream inputs, the fourth threshold generator having an output to supply the fourth threshold (a01) responsive to the long-term average.

14. The system of claim 13 wherein the averaging circuit further includes:

a third threshold generator having an input connected to the output of the non-causal circuit and an input to accept the NRZ data stream input, the third threshold generator tracking the NRZ data stream inputs to maintain an overall long-term average of the NRZ data stream inputs, the third threshold generator having an output to supply the third threshold (Vopt) responsive to the overall long-term average.

15. The system of claim 14 wherein the multi-threshold circuit accepts an NRZ data stream encoded with forward error correction (FEC);

and,

the system further comprising;

a forward error correction (FEC) circuit having an input to receive the first bit value from the non-causal circuit, the FEC circuit decoding the incoming data stream, correcting bit values in response to the decoding, and determining “

0”

bit and “

1”

bit value errors, the FEC circuit having an output connected to the averaging circuit to supply threshold adjustments in response to the determined “

1” and

“

0”

bit value errors.

16. The system of claim 13 further comprising:

a third threshold generator having an input connected to the outputs of the second and fourth threshold generators, the third threshold generator having an output to supply the third threshold (Vopt) approximately midway between the second and fourth thresholds.