Configurable integrated circuit with offset connections

• US 7,468,614 B2
• Filed: 02/15/2007
• Issued: 12/23/2008
• Est. Priority Date: 06/30/2004
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Rohe, Andre, Teig, Steven
• Primary Examiner(s): Chang, Daniel D
• Application Number:
  US11/675,620
• Publication Number:
  US 20070241789A1
• Time in Patent Office: 677 Days
• Field of Search: 326/38, 326/39, 326/41, 326/47, 326/101
• US Class Current: 326/41
• CPC Class Codes: H03K 19/17736 Structural details of routing resources

Abstract

Some embodiments of the invention provide an configurable integrated circuit (“IC”). This IC has at least fifty configurable nodes arranged in an array that several rows and columns. The IC also has several direct offset connections, where each particular direct offset connection connects two offset nodes that are neither in the same column nor in the same row in the array. In some embodiments, several direct connections do not include any intervening circuits. On the other hand, in some embodiments, several direct connections have intervening circuits, which differ from the nodes in the array.

Claims

1. An integrated circuit (“

IC”

) comprising;

a set of at least fifty configurable nodes arranged in an array having a plurality of rows and a plurality of columns; and

a plurality of direct offset connections, wherein each particular direct offset connection connects two offset nodes that are neither in the same column nor in the same row in the array, wherein at least one direct offset connection of said plurality of direct offset connections comprises an intervening buffer circuit but does not comprise an intervening routing circuit, and wherein said intervening buffer circuit is not inside either of said two offset nodes.

2. The IC of claim 1, wherein each of said plurality of direct offset connections comprises a set of wire segments and a set of vias.

3. The IC of claim 1, wherein none of the plurality of direct offset connections comprises intervening circuits that are not buffer circuits.

4. The IC of claim 1, wherein none of said direct offset connections comprise an intervening routing circuit, and wherein a subset of said plurality of direct offset connections comprises intervening circuits that are not buffer circuits.

5. The IC of claim 1, wherein each of the configurable nodes is a configurable circuit for configurably performing a set of operations.

6. The IC of claim 1, wherein each of a plurality of configurable nodes comprises more than one configurable circuit.

7. The IC of claim 1, wherein a plurality of configurable nodes in the array have the same set of circuit elements and the same wiring between the circuit elements.

8. The IC of claim 1, wherein each of a plurality of configurable nodes that is connected to another configurable node by a direct offset connection is also connected to at least one additional configurable node that is in the same column or same row as the configurable node.

9. The IC of claim 1, wherein a plurality of pairs of configurable nodes are neighboring.

10. The IC of claim 1, wherein each of a plurality of offset pairs of nodes is a pair of nodes that are separated in the array by at least two rows or two columns.

11. An electronic device comprising an integrated circuit (IC), said IC comprising:

a set of at least fifty configurable nodes arranged in an array having a plurality of rows and a plurality of columns; and

a plurality of direct offset connections, wherein each particular direct offset connection connects two offset nodes that are neither in the same column nor in the same row in the array, wherein at least one direct offset connection of said plurality of direct offset connections comprises an intervening buffer circuit but does not comprise an intervening routing circuit, and wherein said intervening buffer circuit is not inside either of said two offset nodes.

12. The electronic device of claim 11, wherein each of said plurality of direct offset connections comprises a set of wire segments and a set of vias.

13. The electronic device of claim 11, wherein none of the plurality of direct offset connections comprises intervening circuits that are not buffer circuits.

14. The electronic device of claim 11, wherein none of said direct offset connections comprise an intervening routing circuit, and wherein a subset of said plurality of direct offset connections comprises intervening circuits that are not buffer circuits.

15. The electronic device of claim 11, wherein each of the configurable nodes is a configurable circuit for configurably performing a set of operations.

16. The electronic device of claim 11, wherein each of a plurality of configurable nodes comprises more than one configurable circuit.

17. The electronic device of claim 11, wherein a plurality of configurable nodes in the array have the same set of circuit elements and the same wiring between the circuit elements.

18. The electronic device of claim 11, wherein each of a plurality of configurable nodes that is connected to another configurable node by a direct offset connection is also connected to at least one additional configurable node that is in the same column or same row as the configurable node.

19. The electronic device of claim 11, wherein a plurality of pairs of configurable nodes are neighboring.

20. The electronic device of claim 11, wherein each of a plurality of offset pairs of nodes is a pair of nodes that are separated in the array by at least two rows or two columns.