Test apparatus for mixed-signal semiconductor device

• US 7,472,321 B2
• Filed: 01/20/2005
• Issued: 12/30/2008
• Est. Priority Date: 07/15/2004
• Status: Expired due to Fees

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Chun, Byoung-Ok
• Primary Examiner(s): Chung; Phung M
• Application Number:
  US11/040,132
• Publication Number:
  US 20060015785A1
• Time in Patent Office: 1,440 Days
• Field of Search: 714/724, 714733-734, 714/30, 714/740, 714/799, 324/765, 716/4, 702/122
• US Class Current: 714/724
• CPC Class Codes: G01R 31/3167 Testing of combined analog and digital circuits testing ADC's H03M1/1071
• CPC Class Codes: G01R 31/31924 Voltage or current aspects, e.g. driver, receiver

Abstract

A test apparatus for a mixed-signal semiconductor device that includes a plurality of event tester modules including analog and digital signal tester boards, a test head for event tester modules, a performance board including a socket for a DUT, a test fixture including a connection means, an option circuit for when the DUT is a mixed-signal integrated circuit including an analog and digital function blocks, a tester controller controlling the overall operation, and a switching parallel connection circuit sequentially connecting a single event tester board with a plurality of the DUTs. The event tester board and the DUTs are connected by a group unit. The number of parallel test is increased by an improved tester board or an improved performance board without the use of an extra event tester board for an analog signal test.

Claims

1. A test apparatus for testing mixed-signal semiconductor devices under test (DUTs) that include an analog function block and a digital function block, the test apparatus comprising:

a tester module including a plurality of event tester boards, the event tester boards including analog signal tester boards and digital signal tester boards;

a test head to receive the tester module;

a performance board that includes a plurality of sockets for the DUTs;

a test fixture including connection means, the connection means electrically connecting the performance board and the tester module to the DUTs and to the event tester boards;

a test controller for controlling an overall operation of the test apparatus; and

a switching parallel connection circuit for sequentially connecting each one of the event tester boards with a plurality of the DUTs.

2. The test apparatus of claim 1, wherein the switching parallel connection circuit is in the performance board.

3. The test apparatus of claim 1, wherein the performance board includes an offset supply circuit.

4. The test apparatus of claim 3, wherein the offset supply circuit includes an offset adjustment circuit and a direct path, the offset adjustment circuit having, a low frequency signal source, a DC level source, a first OP amplifier and a second OP amplifier, the first OP amplifier using the low frequency signal source and the DC level as inputs and the second OP amplifier using the input of the first OP amplifier as one input and an output of the second OP amplifier as the other input, the direct path directly connecting the low frequency signal source and an output of the performance board.

5. The test apparatus of claim 1, wherein the event tester boards have a low frequency signal source function and a low frequency signal digitizer function.

6. The test apparatus of claim 5, the event tester boards connected to an input and output of the DUTs and the test controller calculates the phase difference between an input signal phase and an output signal phase by a measured value.

7. The test apparatus of claim 1, wherein the event tester boards comprise no more than four event tester boards having analog source/digitizer functions, each event tester board is connected to a set of two DUTs, and sets of two DUTs are tested in two sets of tests by a switching operation of the switching parallel connection circuit.

8. The test apparatus of claim 1, wherein the DUTs are System On Chip (SOC) semiconductor devices.

9. The test apparatus of claim 1, further comprising an option circuit corresponding to the DUTs when the DUTs are a mixed-signal integrated circuit including an analog function block and a digital function block.

11. The test apparatus of claim 9, wherein the switching parallel connection circuit is part of the performance board.

12. The test apparatus of claim 9, wherein the performance board includes an offset supply circuit.

13. The test apparatus of claim 12, wherein the offset supply circuit includes an offset adjustment circuit and a direct path, the offset adjustment circuit having, a low frequency signal source, a DC level source, a first OP amplifier and a second OP amplifier, the first OP amplifier using the low frequency signal source and the DC level as inputs and the second OP amplifier using the input of the first OP amplifier as one input and an output of the second OP amplifier as the other input, the direct path directly connecting the low frequency signal source and an output of the performance board.

10. A test apparatus for testing mixed-signal semiconductor devices under test (DUTs) that include an analog function block and a digital function block, the test apparatus comprising:

a tester module including a plurality of event tester boards, the plurality of event tester boards including analog signal tester boards and digital signal tester boards;

a performance board that includes a plurality of sockets for the DUTs;

a test fixture including connection means, the connection means electrically connecting the performance board and the tester module to the DUTs and to the event tester boards;

a test controller for controlling an overall operation of the test apparatus; and

a switching parallel connection circuit for sequentially connecting each one of the event tester boards with a plurality of the DUTs.

14. The test apparatus of claim 10, further comprising an option circuit corresponding to the DUTs when the DUTs are a mixed-signal integrated circuit including an analog function block and a digital function block.

15. A test apparatus for testing a plurality of mixed-signal semiconductor devices under test (DUTs) that output analog signals and digital signals, the test apparatus comprising:

event tester boards for testing the analog signals and for testing the digital signals;

a performance board that includes a plurality of sockets to receive the DUTs;

means for electrically connecting the performance board to the DUTs and to the event tester boards;

parallel switching means for sequentially connecting each one of the event tester boards with some of the DUTs; and

a tester controller for controlling the overall operation of the test apparatus.

16. The test apparatus of claim 15, wherein the performance board includes an offset supply circuit, the offset supply circuit including an offset adjustment circuit and a direct path, the offset adjustment circuit having, a low frequency signal source, a DC level source, a first OP amplifier and a second OP amplifier, the first OP amplifier using the low frequency signal source and the DC level as inputs and the second OP amplifier using the input of the first OP amplifier as one input and an output of the second OP amplifier as the other input, the direct path directly connecting the low frequency signal source and an output of the performance board.

17. The test apparatus of claim 15, further comprising an option circuit corresponding to the DUTs when the DUTs are a mixed signal integrated circuit including an analog function block and a digital function block.