Memory systems with column read to an arithmetic operation circuit, pattern detector circuits and methods and computer program products for the same

• US 7,477,186 B2
• Filed: 10/11/2005
• Issued: 01/13/2009
• Est. Priority Date: 10/11/2005
• Status: Expired due to Fees

• Current Assignee: Sony Ericsson Mobile Communications USA Incorporated (Sony Group Corp.)
• Original Assignee: Sony Ericsson Mobile Communications USA Incorporated (Sony Group Corp.)
• Inventors: Camp, William O. Jr.
• Primary Examiner(s): Tarcza; Thomas H
• Assistant Examiner(s): LIU, HARRY K
• Application Number:
  US11/247,771
• Publication Number:
  US 20070080856A1
• Time in Patent Office: 1,190 Days
• Field of Search: 34235701-35717, 375/240.16, 341/156
• US Class Current: 342/357.77
• CPC Class Codes: G01S 19/30 code related G01S19/246 takes precedence
• CPC Class Codes: G01S 19/37 Hardware or software details of the signal processing chain
• CPC Class Codes: G11C 2207/104 Embedded memory devices, e.g. memories with a processing device on the same die or ASIC memory designs
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

Memory systems include an array of storage cells arranged in a row and column arrangement. A plurality of data write lines coupled to the array are configured to supply data into a selected row of the array. A plurality of data read lines coupled to the array are configured to receive data from a selected column of the array in a single read operation. An arithmetic operation circuit coupled to the plurality of data read lines is configured to generate a result value based on data read from the storage cells of a selected column of the array. Methods of detecting a pattern, such as a color code pattern, are also provided.

Claims

1. A memory system, comprising:

an array of storage cells arranged in a row and column arrangement;

a plurality of data write lines coupled to the array and configured to supply data into a selected row of the array;

a plurality of data read lines coupled to the array and configured to receive data from a plurality of cells of a selected column of the array in a single read operation;

an arithmetic operation circuit coupled to the plurality of data read lines that is configured to generate a result value based on data read from the storage cells of a selected column of the array, wherein the arithmetic operation circuit comprises a pattern detector configured to detect a pattern based on a comparison of the data read from the storage cells of the selected column of the array to a candidate pattern and to provide a pattern detect signal as the result value; and

a control circuit configured to select the storage cells in a selected row of the array responsive to a write address input signal by coupling the data write lines to the storage cells in the selected row and to select the storage cells in a selected column of the array responsive to a read address input signal by coupling the data read lines to the storage cells in the selected column to provide data from the storage cells in the selected column to the arithmetic operation circuit.

2. The memory system of claim 1, wherein the write lines are substantially orthogonal to the read lines.

3. The memory system of claim 2, further comprising a second plurality of data read lines coupled to the array and configured to receive data from a selected row of the array in a single read operation.

4. The memory system of claim 1, wherein the pattern detector is configured to detect a color code pattern from a Global Positioning System (GPS) satellite and wherein the pattern detect signal comprises an identification of the GPS satellite when the comparison indicates that data read corresponds to a candidate pattern associated with the GPS satellite.

5. The memory system of claim 4, wherein the control circuit is configured to write data corresponding to acquired data from a plurality of sequential chips of the color code pattern from a first sample of a received signal in a first row of the array and from subsequent samples in subsequent rows of the array to provide a plurality of data associated with respective ones of the sequential chips in corresponding columns of the array and wherein the pattern detector is configured to determine an energy associated with the sequential chips based on data read from a plurality of selected columns of the array to determine if the data read from the array corresponds to the candidate pattern associated with the GPS satellite.

6. A GPS circuit including the memory system of claim 5, further comprising:

a receiver configured to receive a location detection signal from the GPS satellite to provide a received signal; and

a controller configured to repeatedly sample the received signal at a candidate start time and at a chip rate of the candidate pattern associated with the GPS satellite to generate a plurality of sets of data samples and to store the plurality of sets of data samples in the storage cells of selected rows of the array, wherein each of the data sets is stored in an associated row of the array selected by the controller in a single read operation.

7. The GPS circuit of claim 6, wherein the controller is further configured to determine a pseudo-range to the GPS satellite based on the received signal and the identification of the GPS satellite.

8. The GPS circuit of claim 7, wherein the array of storage cells includes a number of rows corresponding to a coherent integration period of the GPS circuit and a number of columns corresponding to a number of data samples in a set of data samples.

9. The memory system of claim 5, wherein the pattern detector is configured to compare the data read from the array to a plurality of candidate patterns associated with different GPS satellites.

10. The memory system of claim 1, wherein the arithmetic operation circuit comprises a summer configured to sum the data read from the storage cells of the selected column of the array and to provide the sum as the result value.

11. The memory system of claim 10, wherein the arithmetic operation circuit further comprises a comparator configured to compare the sum result value to a reference value and to provide a result of the comparison as the result value.

12. The memory system of claim 11, wherein the arithmetic operation circuit is configured to store the sum result value and/or the comparison result value.

13. A mobile device including the memory system of claim 3 and a GPS receiver coupled thereto.

14. The mobile device of claim 13, further comprising a transceiver configured to communicate with a wide area cellular communications network.