Method and apparatus for displaying data from multiple frame buffers on one or more display devices

• US 7,477,205 B1
• Filed: 11/05/2002
• Issued: 01/13/2009
• Est. Priority Date: 11/05/2002
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Donovan, Walter E., de Waal, Abraham B.
• Primary Examiner(s): Caschera; Antonio A
• Application Number:
  US10/288,601
• Time in Patent Office: 2,261 Days
• Field of Search: 345/1.1, 345/539, 345536-540, 345/545, 345/565, 345531-532, 345544-551
• US Class Current: 345/1.3
• CPC Class Codes: G06F 3/1431 using a single graphics controller
• CPC Class Codes: G06F 3/1438 using more than one graphics controller
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/045 Zooming at least part of an image, i.e. enlarging it or shrinking it
• CPC Class Codes: G09G 2340/12 Overlay of images, i.e. displayed pixel being the result of switching between the corresponding input pixels
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/391 Resolution modifying circuits, e.g. variable screen formats
• CPC Class Codes: G09G 5/397 Arrangements specially adapted for transferring the contents of two or more bit-mapped memories to the screen simultaneously, e.g. for mixing or overlay G09G5/02 takes precedence

Abstract

A computer system including a processor, a display, and a graphics unit coupled between the processor and the display, in which the processor is configured to perform multi-display operations which generate multiple frames of display data for simultaneous display, and a graphics unit for use in such a system. Typically, the graphics unit includes graphics memory that includes at least two frame buffers, and the processor operates as if it were independently asserting multiple streams of display data to multiple frame buffers for driving multiple displays independently. Another aspect of the invention is a system that displays data from a frame buffer on a screen. The frame buffer holds data indicative of a virtual desktop that is larger than can be displayed on the screen or available portion thereof, the system can display on the screen any of a number of different subsets of the frame buffer data, each subset indicative of a different portal of the desktop, and the system includes a processor including texture processing circuitry operable to filter a subset of the frame buffer data that is indicative of a portal to be displayed.

Claims

1. A computer system, including:

a processor;

at least one display device; and

a graphics unit coupled between the processor and the at least one display device, the graphics unit including graphics memory defining at least two frame buffers,

wherein the processor is configured to operate in a mode to perform multi-display operations independent of how many display devices are coupled to the graphics unit, the processor in said mode generating at least two streams of display data for simultaneous display,

wherein driver software for the graphics unit determines whether the at least one display device that is coupled to the graphics unit includes only a first display device or includes the first display device and a second display device, and places the graphics unit in a first mode when only the first display device is coupled to the graphics unit and in a second mode when the first display device and the second display device are coupled to the graphics unit,

wherein the graphics unit is configured to store each stream of the at least two streams of display data in a corresponding frame buffer of the at least two frame buffers and includes a frame combining circuitry connected separately to each of the at least two frame buffers, and

wherein the frame combining circuitry has inputs coupled to receive display data from the at least two frame buffers and at least a first output coupled to the first display device, and the frame combining circuitry is operable in the first mode in which it generates an image by combining display data from each of the at least two frame buffers and asserts the image to the first output for display on the first display device, and is operable in the second mode in which it passes first display data from a first frame buffer of the at least two frame buffers to the first output for display on the first display device and passes second display data from a second frame buffer of the at least two frame buffers to a second output that is physically separate from the first output and coupled to a second display device of the at least one display device for simultaneous display with the first display data on the first display device.

2. The system of claim 1, wherein the image includes a filtered version of at least a subset of the display data in at least one of the at least two frame buffers.

3. The system of claim 1, wherein the image includes at least a subset of the display data in each of the at least two frame buffers.

4. The system of claim 1, wherein the graphics unit further includes a pipelined graphics processor configured to generate the display data to be written to the at least two frame buffers.

5. The system of claim 1, wherein the processor is a pipelined graphics processor configured to generate independently the at least two streams of display data to be written to the at least two frame buffers.

6. The system of claim 1, wherein the first display device has a screen and the frame combining circuitry is operable in the first mode to assert the image to the first output for display on the screen with display data from each of the at least two frame buffers displayed on a different region of the screen.

7. The system of claim 1, wherein the first display device has a screen and the frame combining circuitry operates in the first mode under software control to generate the image such that when the image is displayed, display data from different ones of the at least two frame buffers are displayed with controllable relative positions on the screen.

8. The system of claim 1, wherein the graphics unit comprises a texture processing subsystem, and the graphics unit is configured to assert display data from at least one of the at least two frame buffers to the texture processing subsystem to cause the texture processing subsystem to generate filtered data by filtering the display data, and to store the filtered data in the graphics memory and to assert the filtered data to the first display device.

9. The system of claim 1, wherein the processor has a texture processing subsystem, and the graphics unit is configured to assert display data from at least one of the at least two frame buffers to the texture processing subsystem to cause the texture processing subsystem to generate filtered data by filtering the display data, to receive the filtered data, to store said filtered data in the graphics memory, and to assert the filtered data from the graphics memory to the first display device.

10. The system of claim 1, wherein the graphics unit is configured to assert the display data from at least one of the at least two frame buffers to the processor, and the processor is configured to generate filtered data by filtering the display data, and wherein the graphics unit is further configured to receive the filtered data, store the filtered data in the graphics memory, and assert the filtered data from the graphics memory to the first display device.

11. The system of claim 1, wherein the processor and the graphics unit are configured to respond to an operating system alert by causing an indication of the alert to be displayed on the first display device such that the indication automatically overlays whatever else is being displayed on the first display device.

12. The system of claim 1, wherein the processor and the graphics unit are configured to respond to an operating system alert by displaying on the first display device a sequence of images that pan to a displayed indication of the alert.

13. The system of claim 1, wherein the first display device has a screen, and the processor and graphics unit are configured to operate under control of operating system software and to respond to an operating system alert by causing an alert indication to be displayed in a position on the screen specified by the operating system software.

14. The system of claim 1, wherein the first display device has a screen, and the processor and graphics unit are configured to operate under control of operating system software and to respond to an operating system alert by causing an alert indication to be displayed in a position on the screen other than a screen position specified by the operating system software.

15. The system of claim 1, wherein the frame combining circuitry is further configured to pass additional display data, received from an additional frame buffer of the at least two frame buffers, to an additional output that is physically separate from the first output and the second output and coupled to an additional display device of the at least one display device for simultaneous display with the first display data on the first display device and the second display data on the second display device.