Continuous application and decompression of test patterns to a circuit-under-test

• US 7,478,296 B2
• Filed: 01/29/2003
• Issued: 01/13/2009
• Est. Priority Date: 11/23/1999
• Status: Expired due to Term

• Current Assignee: Siemens Industry Software Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Mukherjee, Nilanjan, Tyszer, Jerzy, Rajski, Janusz, Kassab, Mark
• Primary Examiner(s): Chung; Phung M
• Application Number:
  US10/354,633
• Publication Number:
  US 20030120988A1
• Time in Patent Office: 2,176 Days
• Field of Search: 714/738, 714/726, 714/724, 714/733, 714/734, 714/727, 714/728, 714/729, 714/30
• US Class Current: 714/726
• CPC Class Codes: G01R 31/31813 Test pattern generators
• CPC Class Codes: G01R 31/318335 Test pattern compression or decompression compression or decompression of scan patterns G01R31/318547; compression or decompression hardware G01R31/31921
• CPC Class Codes: G01R 31/318547 Data generators or compressors

Abstract

A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear feedbackstate machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received. The circuit further includes scan chains for testing circuit logic, the scan chains coupled to the decompressor and adapted to receive the decompressed test pattern.

Claims

1. An apparatus to test an integrated circuit, comprising:

a linear feedback shift register (LFSR) within the integrated circuit;

automatic testing equipment located external to the integrated circuit; and

a plurality of registers within the integrated circuit and coupled between outputs of the automatic testing equipment and inputs of the LFSR.

2. The apparatus of claim 1, wherein the registers receive compressed test pattern bits in parallel from the automatic testing equipment.

3. The apparatus of claim 1, further including a phase shifter coupled to the LFSR.

4. The apparatus of claim 1, further including scan chains within the integrated circuit and a phase shifter coupled between the LFSR and the scan chains.

5. The apparatus of claim 1, wherein the registers receive compressed test pattern bits in parallel from the automatic testing equipment and shift the compressed test pattern bits to the LFSR while the LFSR decompresses the compressed test pattern.

6. An apparatus to test an integrated circuit, comprising:

a plurality of registers within the integrated circuit;

a phase shifter within the integrated circuit; and

a linear feedback shift register (LFSR) having a plurality of inputs coupled to respective outputs of the plurality of registers and having a plurality of outputs coupled to respective inputs of the phase shifter.

7. The apparatus of claim 6 further including automatic testing equipment (ATE) located externally to the integrated circuit and coupled to respective inputs of the plurality of registers.

8. The apparatus of claim 6, further including scan chains coupled to the phase shifter.

9. The apparatus of claim 6, wherein the phase shifter is formed from only XOR gates.

10. The apparatus of claim 6, further including automatic testing equipment (ATE) located externally to the integrated circuit and coupled to the registers such that the plurality of registers is capable of receiving compressed test pattern bits in parallel from the ATE.

11. The apparatus of claim 6, wherein the plurality of registers are shift registers.

12. A method of testing an integrated circuit, comprising:

loading a register within the integrated circuit with a compressed test pattern;

transferring the compressed test pattern from an output of the register to an input of a linear feedback shift register (LFSR); and

decompressing the compressed test pattern, wherein the transferring and the decompressing of the compressed test pattern occur simultaneously.

13. The method of claim 12, further including passing the decompressed test pattern through a phase shifter.

14. The method of claim 12, wherein the loading is a parallel load of the compressed test pattern from external automatic testing equipment (ATE).

15. The method of claim 12, further including loading scan chains with the decompressed test pattern after the decompressed test pattern passes through a phase shifter.

16. The method of claim 12, wherein loading of the register is performed in parallel, and wherein transferring includes serially shifting the compressed test pattern to a decompressor.