Membrane 3D IC fabrication
First Claim
1. Circuitry comprising:
- a first integrated circuit having first active devices;
a second integrated circuit having second active devices, a plurality of metal interconnect layers, and at least one elastic dielectric layer at least in part between two of the plurality of metal interconnect layers, wherein at least one of the plurality of metal interconnect layers interconnects a plurality of the second active devices underneath the at least one elastic dielectric layer; and
a plurality of bonds formed between the first integrated circuit and second integrated circuit wherein the bonds provide a primary means of adhesion between the first integrated circuit and the second integrated circuit, wherein the at least one elastic dielectric layer is substantially flexible, and wherein the at least one elastic dielectric layer has a stress of at least one of less than about 8×
108 dynes/cm2 and 2 to 100 times less than the fracture strength of the at least one elastic dielectric layer.
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Accused Products
Abstract
General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.
230 Citations
21 Claims
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1. Circuitry comprising:
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a first integrated circuit having first active devices; a second integrated circuit having second active devices, a plurality of metal interconnect layers, and at least one elastic dielectric layer at least in part between two of the plurality of metal interconnect layers, wherein at least one of the plurality of metal interconnect layers interconnects a plurality of the second active devices underneath the at least one elastic dielectric layer; and a plurality of bonds formed between the first integrated circuit and second integrated circuit wherein the bonds provide a primary means of adhesion between the first integrated circuit and the second integrated circuit, wherein the at least one elastic dielectric layer is substantially flexible, and wherein the at least one elastic dielectric layer has a stress of at least one of less than about 8×
108 dynes/cm2 and 2 to 100 times less than the fracture strength of the at least one elastic dielectric layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification