Method for manufacturing semiconductor device
First Claim
Patent Images
1. A method for manufacturing and operating a semiconductor device, comprising:
- forming a P+ buried layer;
forming an N drift region formed over the P+ buried layer;
forming a cathode, a gate, and an anode over the P+ buried layer, the cathode, the gate, and the anode being spaced apart from each another;
forming a P+ cathode below the cathode and over the P+ buried layer;
forming a P-base area below the gate and over the P+ buried layer, the P-base are being spaced apart from the P+ cathode;
forming a P+ anode below the anode and over the P+ buried layer;
forming a N+ cathode over the P+ buried layer and between the cathode and gate, wherein the P-base area is not formed below the N+ cathode; and
injecting a hole current into the N drift region while a constant voltage is applied to the P+ anode, such that a majority of the hole current passes through the P+ cathode of via the P+ buried layer.
6 Assignments
0 Petitions
Accused Products
Abstract
A method for manufacturing a semiconductor device includes steps of injecting a hole current into an N drift region while a constant voltage is applied to a P+ anode of a lateral insulated gate bipolar transistor, such that a majority of the hole current passes through a P+ cathode of the lateral insulated gate bipolar transistor via a P+ buried layer. Therefore, a hole-current path located under an N+ cathode area of a LIGBT structure is eliminated, thus securing sufficient latch-up current density.
121 Citations
1 Claim
-
1. A method for manufacturing and operating a semiconductor device, comprising:
-
forming a P+ buried layer; forming an N drift region formed over the P+ buried layer; forming a cathode, a gate, and an anode over the P+ buried layer, the cathode, the gate, and the anode being spaced apart from each another; forming a P+ cathode below the cathode and over the P+ buried layer; forming a P-base area below the gate and over the P+ buried layer, the P-base are being spaced apart from the P+ cathode; forming a P+ anode below the anode and over the P+ buried layer; forming a N+ cathode over the P+ buried layer and between the cathode and gate, wherein the P-base area is not formed below the N+ cathode; and injecting a hole current into the N drift region while a constant voltage is applied to the P+ anode, such that a majority of the hole current passes through the P+ cathode of via the P+ buried layer.
-
Specification
-
- Resources
Litigation Campaign Assessment
Thank you for your request. You will receive a custom alert email when the Litigation Campaign Assessment is available.
×
-
Current AssigneeTaiwan Semiconductor Manufacturing Company Limited
-
Original AssigneeDONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
-
InventorsSung, Woong Je
-
Primary Examiner(s)Pert; Evan
-
Assistant Examiner(s)QUINTO, KEVIN V
-
Application NumberUS11/320,903Publication NumberTime in Patent Office1,124 DaysField of Search257/107, 257/133, 257/139, 257/141, 257/499, 257/557, 257/558, 257/559, 257/560, 257/561, 257/562, 257/563, 257/564, 257/E21.424, 257/E21.425, 257/E21.426, 257/E21.427, 257/E21.428, 438/309, 438/312, 438/313, 438/316, 438/322, 438/327, 438/335US Class Current438/335CPC Class CodesH01L 29/7393 Insulated gate bipolar mode...
