Metal wiring and method of manufacturing the same, and metal wiring substrate and method of manufacturing the same

• US 7,482,274 B2
• Filed: 04/14/2005
• Issued: 01/27/2009
• Est. Priority Date: 07/27/2001
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Suzawa, Hideomi, Ono, Koji
• Primary Examiner(s): Dang; Phuc T
• Assistant Examiner(s): Tran; Thanh Y
• Application Number:
  US11/105,917
• Publication Number:
  US 20050230838A1
• Time in Patent Office: 1,384 Days
• Field of Search: 438/669, 438/671, 438/685, 438/688, 438/694, 438/486, 438/482, 438/164, 438/166, 438/689, 438/708, 438/709, 438/734, 438/487, 438/FOR.439, 257/784, 257/786, 257/734, 257/758, 257/763, 257/765, 257/771, 257/64, 257/70, 257/75, 257/E21.02
• US Class Current: 438/689
• CPC Class Codes: C23F 4/00 Processes for removing metallic material from surfaces, not provided for in group C23F1/00 or C23F3/00
• CPC Class Codes: H01B 1/02 mainly consisting of metals or alloys
• CPC Class Codes: H01B 13/0006 for reducing the size of conductors or cables
• CPC Class Codes: H01B 13/0036 Details
• CPC Class Codes: H01B 5/14 comprising conductive layers or films on insulating-supports
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle α in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.

Claims

1. A method of manufacturing a semiconductor device comprising:

forming an insulating layer over a substrate;

forming an amorphous semiconductor layer on the insulating layer;

forming a crystalline semiconductor layer on the insulating layer by crystallizing the amorphous semiconductor film;

forming at least one semiconductor island by patterning the crystalline semiconductor layer;

forming a gate insulating film on the semiconductor island;

forming at least first and second conductive films on the gate insulating film;

forming a resist pattern on the second conductive film;

performing a first etching treatment for the first and second conductive films;

performing a second etching treatment for the first and second conductive films, thereby etching the second conductive film selectively;

forming impurity regions in the semiconductor island by doping impurity elements; and

forming an interlayer insulating film over the first and second conductive films and the semiconductor island,

wherein the first etching treatment is performed by ICP etching under conditions that bias power density is 0.5 W/cm² or more, etching rate of the resist pattern is 350 nm/min or more, and selective ratio of the second conductive film and the resist pattern is 2 or more.

2. A method according to claim 1, wherein the second conductive film is a thin film selected from the group consisting of a tungsten film, a metal compound film with a tungsten compound as its main ingredient, and a metal alloy film with a tungsten alloy as its main ingredient, and a thin film selected from the group consisting of an aluminum film, a metal compound film with an aluminum compound as its main ingredient, and a metal alloy film with an aluminum alloy as its main ingredient.

3. The method according to claim 1, wherein the amorphous semiconductor layer is crystallized by a heating crystallization method using RTA.

4. The method according to claim 1, wherein the amorphous semiconductor layer is crystallized by furnace annealing.

5. The method according to claim 1, wherein the amorphous semiconductor layer is crystallized by a laser crystallization method.

6. The method according to claim 1, wherein during the first etching treatment, taper angles of the first and second conductive films are controlled by changing a bias power density of an etching apparatus.

7. The method according to claim 1, wherein etching rate of the second conductive film is 150 nm/mim or more.

8. A method of manufacturing a semiconductor device comprising:

forming an insulating layer over a substrate;

forming an amorphous semiconductor layer on the insulating layer;

forming a crystalline semiconductor layer by crystallizing the amorphous semiconductor film;

forming at least one semiconductor island by patterning the crystalline semiconductor layer;

forming a gate insulating film on the semiconductor island;

forming at least first and second conductive films on the gate insulating film;

forming a resist pattern on the second conductive film; and

performing a first etching treatment for the first and second conductive films under first and second etching conditions;

performing a second etching treatment for the second conductive film, selectively;

forming impurity regions in the semiconductor island by doping impurity elements;

forming an interlayer insulating film over the first and second conductive films and the semiconductor island; and

forming wirings over the interlayer insulating film, the wirings electrically connected to the impurity regions in the semiconductor island, respectively,

wherein the first etching treatment is performed by ICP etching under conditions that bias power density is 0.5 W/cm² or more, etching rate of the resist pattern is 350 nm/mim or more, and selective ratio of the second conductive film and the resist pattern is 2 or more.

9. A method according to claim 8, wherein the second conductive film is a thin film selected from the group consisting of a tungsten film, a metal compound film with a tungsten compound as its main ingredient, and a metal alloy film with a tungsten alloy as its main ingredient, or a thin film selected from the group consisting of an aluminum film, a metal compound film with an aluminum compound as its main ingredient, and a metal alloy film with an aluminum alloy as its main ingredient.

10. The method according to claim 8, wherein the amorphous semiconductor layer is crystallized by a heating crystallization method using RTA.

11. The method according to claim 8, wherein the amorphous semiconductor layer is crystallized by furnace annealing.

12. The method according to claim 8, wherein the amorphous semiconductor layer is crystallized by a laser crystallization method.

13. The method according to claim 8, wherein during the first etching treatment, taper angles of the first and second conductive films are controlled by changing a bias power density of an etching apparatus.

14. The method according to claim 8, wherein etching rate of the second conductive film is 150 nm/min or more.

15. A method of manufacturing a semiconductor device comprising:

forming an insulating layer over a substrate;

forming an amorphous semiconductor layer on the insulating layer;

forming a crystalline semiconductor layer by crystallizing the amorphous semiconductor film;

forming at least one semiconductor island by patterning the crystalline semiconductor layer;

forming a gate insulating film on the semiconductor island;

forming at least first and second conductive films on the gate insulating film;

forming a resist pattern on the second conductive film;

performing a first etching treatment for the first and second conductive films under first and second etching conditions;

performing a second etching treatment for the second conductive film, selectively;

forming impurity regions in the semiconductor island by doping impurity elements;

forming an interlayer insulating film over the first and second conductive films and the semiconductor island; and

forming wirings and a pixel electrode over the interlayer insulating film, the wirings and the pixel electrode electrically connected to the impurity regions in the semiconductor island, respectively,

wherein the first etching treatment is performed by ICP etching under conditions that bias power density is 0.5 W/cm² or more, etching rate of the resist pattern is 350 nm/min or more, and selective ratio of the second conductive film and the resist pattern is 2 or more.

16. A method according to claim 15, wherein the second conductive film is a thin film selected from the group consisting of a tungsten film, a metal compound film with a tungsten compound as its main ingredient, and a metal alloy film with a tungsten alloy as its main ingredient, or a thin film selected from the group consisting of an aluminum film, a metal compound film with an aluminum compound as its main ingredient, and a metal alloy film with an aluminum alloy as its main ingredient.

17. The method according to claim 15, wherein the amorphous semiconductor layer is crystallized by a heating crystallization method using RTA.

18. The method according to claim 15, wherein the amorphous semiconductor layer is crystallized by furnace annealing.

19. The method according to claim 15, wherein the amorphous semiconductor layer is crystallized by a laser crystallization method.

20. The method according to claim 15, wherein during the first etching treatment, taper angles of the first and second conductive films are controlled by changing a bias power density of an etching apparatus.

21. The method according to claim 15, wherein etching rate of the second conductive film is 150 nm/min or more.