3D IC method and device

• US 7,485,968 B2
• Filed: 08/11/2005
• Issued: 02/03/2009
• Est. Priority Date: 08/11/2005
• Status: Active Grant

• Current Assignee: Invensas Bonding Technologies, Inc. (Adeia Inc.)
• Original Assignee: Ziptronix Incorporated (Adeia Inc.)
• Inventors: Enquist, Paul M., Tong, Qin-Yi, Fountain, Gaius Gillman Jr.
• Primary Examiner(s): Vu; David
• Application Number:
  US11/201,321
• Publication Number:
  US 20070037379A1
• Time in Patent Office: 1,272 Days
• Field of Search: 257/777, 257/E25.013, 257/E25.027, 257/E25.023, 257/E23.011, 257/E23.063, 257/686, 257/700, 257/701, 438/455
• US Class Current: 257/777
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/08225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/81 using a bump connector
• CPC Class Codes: H01L 2224/81121 Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
• CPC Class Codes: H01L 2224/81201 Compression bonding
• CPC Class Codes: H01L 2224/8123 Polychromatic or infrared lamp heating
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/81931 by chemical means, e.g. etching
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/83894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/9212 Sequential connecting processes
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/01002 : Helium [He]
• CPC Class Codes: H01L 2924/01004 : Beryllium [Be]
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01007 : Nitrogen [N]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01028 : Nickel [Ni]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01042 : Molybdenum [Mo]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01055 : Cesium [Cs]
• CPC Class Codes: H01L 2924/01059 : Praseodymium [Pr]
• CPC Class Codes: H01L 2924/01073 : Tantalum [Ta]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01077 : Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/04953 : TaN
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/12044 : OLED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface. Alternatively, first and/or second contact structures are not exposed at bonding, and a via is etched and filled after bonding to electrically interconnect first and second contact structures and provide electrical access to interconnected first and second contact structure to a surface. Also, a device may be formed in a first substrate, the device being disposed in a device region of the first substrate and having a first contact structure. A via may be etched, or etched and filled, through the device region and into the first substrate before bonding and the first substrate thinned to expose the via, or filled via after bonding.

Claims

1. A structure, comprising:

a first element having a first substrate, a first insulating layer disposed on said first substrate containing silicon and at least one of oxygen and nitrogen, and a first contact structure disposed in said first insulating layer;

a second element having a second substrate, a second insulating layer disposed on said second substrate containing silicon and at least one of oxygen and nitrogen, and a second contact structure disposed in said second insulating layer;

said first insulating layer directly bonded to said second insulating layer;

said first contact structure directly connected to said second contact structure; and

an interconnect structure disposed in a via and connected to said first contact structure.

2. A structure as recited in claim 1, comprising:

said first contact structure being substantially planar with a surface of said first insulating layer.

3. A structure as recited in claim 2, comprising:

said second contact structure being substantially planar with a surface of said second insulating layer.

4. A structure as recited in claim 1, wherein said first contact structure comprises one of copper, tungsten, nickel, and gold.

5. A structure as recited in claim 1, comprising:

each of said first and second contact structures having a polished surface; and

said polished surfaces being in direct contact with each other.

6. A structure as recited in claim 1, wherein:

said first and second contact structures are nominally the same width; and

a portion of an upper surface of said first contact structure is in contact with said second insulating layer.

7. A structure as recited in claim 1, wherein a contact resistance between said first and second contact structures is less than 1 ohm/μ

m².

8. A structure as recited in claim 1, wherein each of said first and second contact structures comprises a thermally-expanded metal contact structure.

9. A structure ad recited in claim 8, wherein each of said first and second contact structures comprises one of copper, tungsten, nickel, and gold.

10. A structure as recited in claim 1, wherein each of said first and second contact structures comprises a metal contact structure with a surface from which a native oxide is removed.

11. A structure as recited in claim 1, comprising:

a third contact structure connected to said first contact structure and disposed in a via in said first insulating material.

12. A structure as recited in claim 11, comprising:

said first contact structure having a planar surface connected to said third contact structure.

13. A structure as recited in claim 11, wherein sides of said via are comprised of a dielectric material.

14. A structure as recited in claim 11, comprising:

said third contact structure comprising a first metal layer formed on said first insulating material and a second metal layer formed on said first metal layer.

15. A structure as recited in claim 11, comprising:

said first element having first and second opposing surfaces;

said first surface bonded to said second element; and

said via extending from said second surface to said first contact structure.

16. A structure as recited in claim 11, wherein:

said first element is bonded to said second element using a direct bonding process.

17. A structure as recited in claim 1, wherein:

said first and second insulating layers are directly bonded.

18. A structure as recited in claim 1, wherein said first element comprises a semiconductor substrate.

19. A structure as recited in claim 1, wherein said first element comprises a semiconductor substrate.

20. A structure, comprising:

a first element having a first substrate, a first upper layer disposed on said first substrate comprising a first insulating region and a first conducting region;

a second element having a second substrate, a second upper layer disposed on said second substrate comprising a second insulating region and a second conducting region;

said first insulating region directly bonded to said second insulating region;

said first conducting region directly connected to said second conducting region; and

at least one of said first and second conducting regions comprises a thermally-expanded metal contact structure.

21. A structure as in claim 20, wherein at least one of said first and second insulating layers further comprises silicon and at least one of oxygen and nitrogen.

22. A structure as in claim 20, wherein at least one of said first and second conducting regions further comprises a contact structure.

23. A structure as in claim 22, wherein said contact structure further comprises multiple contact structures.

24. A structure as in claim 23, further comprising electrical isolation between at least two of said multiple contact structures.

25. A structure as in claim 20, wherein at least one of said first and second substrates further comprises a semiconductor device.

26. A structure as in claim 20, wherein at least one of said first and second substrates further comprises a portion of a semiconductor device.

27. A structure as recited in claim 20, comprising:

said first conducting region being substantially planar with a surface of said first insulating region.

28. A structure as recited in claim 27, comprising:

said second conducting region being substantially planar with a surface of said second insulating region.

29. A structure as recited in claim 20, wherein said first conducting region comprises one of copper, tungsten, nickel, and gold.

30. A structure as recited in claim 20, comprising:

each of said first and second conducting regions having a polished surface; and

said polished surfaces being in direct contact with each other.

31. A structure as recited in claim 20, wherein:

said first and second conducting regions are nominally the same width; and

a portion of an upper surface of said first conducting region is in contact with said second insulating region.

32. A structure as recited in claim 20, wherein a contact resistance between said first and second conducting regions is less than 1 ohm/μ

m².

33. A structure as recited in claim 20, wherein each of said first and second conducting regions comprises a thermally-expanded metal contact structure.

34. A structure as recited in claim 33, wherein each of said first and second conducting regions comprises one of copper, tungsten, nickel, and gold.

35. A structure as recited in claim 20, wherein each of said first and second conducting regions comprises a metal contact structure with a surface from which a native oxide is removed.

36. A structure as recited in claim 20, comprising:

a conductive member connected to said first conducting region and disposed in a via in said first insulating region.

37. A structure as recited in claim 36, comprising:

said first conducting region having a planar surface connected to said conductive member.

38. A structure as recited in claim 36, wherein sides of said via are comprised of a dielectric material.

39. A structure as recited in claim 36, comprising:

said conductive member comprising a first metal layer formed on said first insulating region and a second metal layer formed on said first metal layer.

40. A structure as recited in claim 36, comprising:

said first element having first and second opposing surfaces;

said first surface bonded to said second element; and

said via extending from said second surface to said first conducting region.

41. A structure as recited in claim 20, wherein:

said first element is bonded to said second element using a direct bonding process.