Structure and methods for stress concentrating spacer

• US 7,488,659 B2
• Filed: 03/28/2007
• Issued: 02/10/2009
• Est. Priority Date: 03/28/2007
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dyer, Thomas W.
• Primary Examiner(s): Ghyka; Alexander G
• Assistant Examiner(s): Chang; Leonard
• Application Number:
  US11/692,371
• Publication Number:
  US 20080237726A1
• Time in Patent Office: 685 Days
• Field of Search: 438/50, 438/184, 438/303, 438/938, 438/294, 438/296
• US Class Current: 438/296
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer
• CPC Class Codes: Y10S 438/938 Lattice strain control or utilization

Abstract

A stress-concentrating spacer structure is a stack of an upper gate spacer with a low Young'"'"'s modulus and a lower gate spacer with a high Young'"'"'s modulus. The stacked spacer structure surrounds the gate electrode. The stress-concentrating spacer structure may contact an inner gate spacer that contacts the gate electrode or may directly contact the gate electrode. The upper gate spacer deforms substantially more than the lower gate spacer. The stress generated by the stress liner is thus transmitted primarily through the lower gate spacer to the gate electrode and subsequently to the channel of the MOSFET. The efficiency of the transmission of the stress from the stress liner to the channel is thus enhanced compared to conventional MOSFETs structure with a vertically uniform composition within a spacer.

Claims

1. A method of manufacturing a semiconductor structure, comprising:

forming a gate electrode on a gate dielectric on a semiconductor substrate;

forming a source and drain metal semiconductor alloy on said semiconductor substrate;

forming an L-shaped inner gate spacer that abuts sidewalls of said gate electrode and abuts source and drain regions;

forming a non-conformal lower spacer layer with a first Young'"'"'s modulus on said gate electrode and said semiconductor substrate, wherein said first Young'"'"'s modulus is in a range from about 100 GPa to about 1,000 GPa;

removing a vertical portion of said non-conformal lower spacer layer on said gate electrode and exposing underlying vertical surfaces, whereby a substrate-contacting lower spacer layer is formed directly on said source and drain metal semiconductor alloy and a gate-top-contacting lower spacer layer is formed directly on said gate electrode from remaining portions of said non-conformal lower spacer layer, wherein said exposed underlying vertical surfaces are sidewalls of said L-shaped inner gate spacer;

forming an upper gate spacer with a second Young'"'"'s modulus directly on said exposed underlying vertical surfaces and on said substrate-contacting lower spacer layer, wherein said first Young'"'"'s modulus is greater than said second Young'"'"'s modulus, and wherein said second Young'"'"'s modulus is in a range from 0 GPa to about 100 GPa;

removing said gate-top-contacting lower spacer layer and a portion of said substrate-contacting lower spacer layer that is not covered by said upper gate spacer to form a lower gate spacer directly beneath said upper gate spacer and directly on said L-shaped inner gate spacer, wherein said lower gate spacer does not abut said source and drain region;

forming a stress liner directly on said lower gate spacer and said upper gate spacer;

removing a portion of said stress liner from above the sidewalls of said upper gate spacer;

forming a middle-of-line (MOL) dielectric layer on a remaining portion of said stress liner, wherein said remaining portion is located directly on a source and drain metal semiconductor alloy and said MOL dielectric layer directly contacts said upper gate spacer, and wherein said MOL dielectric layer does not abut said lower gate spacer, said upper gate spacer, or said gate electrode; and

removing said stress liner from above said gate electrode, wherein said MOL dielectric layer abuts a top surface of said gate electrode.