Device and method for controlling refresh rate of memory

• US 7,489,579 B2
• Filed: 06/21/2006
• Issued: 02/10/2009
• Est. Priority Date: 01/25/2006
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Ho, Kuan-Jui
• Primary Examiner(s): Luu; Pho M.
• Application Number:
  US11/425,653
• Publication Number:
  US 20070171751A1
• Time in Patent Office: 965 Days
• Field of Search: 365/126, 365/221, 365/212, 365/222, 365/51, 365/52, 365/189.2, 365/211, 713 1- 2, 713/320
• US Class Current: 365/222
• CPC Class Codes: G06F 13/1636 using refresh
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/40626 Temperature related aspects of refresh operations
• CPC Class Codes: G11C 2211/4061 Calibration or ate or cycle tuning

Abstract

A control device and method are used for adjusting the refresh rate of a memory module in a computer system. The device includes a thermo sensor and a control circuit. In the control method, the thermo sensor actively outputs a temperature change signal in response to the temperature change in the memory module when a capacitor of the memory module incurs an aggravated current leakage due to the temperature rise. Next, the control circuit adjusts the refresh rate in response to the temperature change signal and refreshes the memory module at the refresh rate.

Claims

1. A control device for adjusting a refresh rate of a memory module in a computer system, comprising:

a thermo sensor integrated into the memory module for actively outputting a temperature change signal in response to the temperature change in the memory module; and

a control circuit electrically connected to the memory module and said thermo sensor for adjusting a refresh period for refreshing the memory module in response to the temperature change signal.

2. The control device of claim 1, wherein said thermo sensor is integrated into an electrically erasable programmable read only memory (EEPROM) and said EEPROM is connected to said control circuit via a system management bus (SMBus) and presented as a master device on said SMBus.

3. The control device of claim 1, wherein said control circuit shortens the refresh period when the temperature change signal outputted actively by said thermo sensor is a temperature up signal, and lengthens the refresh period when the temperature change signal outputted actively by said thermo sensor is a temperature down signal.

4. The control device of claim 1, said control circuit further comprising:

a Southbridge chip electrically connected to said thermo sensor for outputting a period change signal in response to the temperature change signal; and

a Northbridge chip electrically connected to said Southbridge chip and the memory module for refreshing the memory module once every the refresh period and adjusting the refresh period in response to the period change signal.

5. The control device of claim 1, said control circuit further comprising a Northbridge chip electrically connected to said thermo sensor and the memory module for refreshing the memory module once every the refresh period and adjusting the refresh period in response to the temperature change signal.

6. The control device of claim 1, wherein the memory module in the computer system is a Dual Inline Memory Module (DIMM).

7. The control device of claim 1, wherein said control circuit, operating in a normal mode, refreshes the memory module once every the refresh period adjusted in response to the temperature change signal outputted actively by said thermo sensor.

8. A control apparatus, for adjusting a refresh rate of a dynamic random access memory (DRAM) module in a computer system, comprising:

a thermo sensor integrated into the DRAM module for actively outputting a temperature change signal when a capacitor of the DRAM module incurs leakage current due to the temperature change; and

a control circuit electrically connected to the DRAM module and said thermo sensor for adjusting a refresh period for refreshing the DRAM module in response to the temperature change signal.

9. The control device of claim 8, wherein said thermo sensor is connected to said control circuit via a SMBus.

10. The control device of claim 8, wherein said control circuit shortens the refresh period when the temperature change signal outputted actively by said thermo sensor is a temperature up signal, and lengthens the refresh period when the temperature change signal outputted actively by said thermo sensor is a temperature down signal.

11. The control device of claim 8, said control circuit further comprising:

a Southbridge chip electrically connected to said thermo sensor for outputting a period change signal in response to the temperature change signal; and

a Northbridge chip electrically connected to said Southbridge chip and the DRAM module for refreshing the DRAM module once every the refresh period and adjusting the refresh period in response to the period change signal.

12. The control device of claim 8, said control circuit further comprising a Northbridge chip electrically connected to said thermo sensor and the DRAM module for refreshing the DRAM module once every the refresh period and adjusting the refresh period in response to the temperature change signal.

13. The control device of claim 8, wherein the DRAM module in the computer system is a DIMM.

14. The control device of claim 8, wherein said control circuit, operating in a normal mode, refreshes the DRAM module once every the refresh period adjusted in response to the temperature change signal outputted actively by said thermo sensor.

15. A control method for adjusting a refresh rate of a memory in a computer system, said computer system comprising a DRAM module, a thermo sensor integrated into the DRAM module and a control circuit disposed in a chipset;

the control method comprising steps of;

the thermo sensor actively outputting a temperature change signal when a capacitor of the DRAM module incurs leakage current due to the temperature change; and

the control circuit refreshing the DRAM module once every refresh period which is adjusted in response to the temperature change signal.

16. The control method of claim 15, wherein the refresh period is shortened when the temperature change signal is a temperature up signal, and the refresh period is lengthened when the temperature change is a temperature down signal.

17. The control method of claim 15, wherein the control circuit receives the temperature change signal via a SMBus.

18. The control method of claim 17, wherein the chipset comprises:

a Southbridge chip for receiving the temperature change signal actively transmitted by the thermo sensor via the SMBus; and

a Northbridge chip for adjusting the refresh period for refreshing the DRAM module in response to the temperature change signal.

19. The control method of claim 17, wherein the chipset comprises a Northbridge chip for receives the temperature change signal transmitted actively by the thermo sensor via the SMBus and adjusting the refresh period for refreshing the DRAM module in response to the temperature change signal.