Mass storage controller with apparatus and method for extending battery backup time by selectively providing battery power to volatile memory banks not storing critical data

• US 7,493,441 B2
• Filed: 03/15/2005
• Issued: 02/17/2009
• Est. Priority Date: 03/15/2005
• Status: Active Grant

• Current Assignee: Dot Hill Systems Corporation (Seagate Technology Holdings Plc)
• Original Assignee: Dot Hill Systems Corporation (Seagate Technology Holdings Plc)
• Inventors: Ashmore, Paul Andrew
• Primary Examiner(s): Bragdon; Reginald G
• Assistant Examiner(s): Mackall; Larry T
• Application Number:
  US11/079,981
• Publication Number:
  US 20060212651A1
• Time in Patent Office: 1,435 Days
• Field of Search: None
• US Class Current: 711/5
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 2212/2228 Battery-backed RAM
• CPC Class Codes: G06F 2212/282 Partitioned cache
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A battery-backed write-caching mass storage controller is disclosed. The controller includes a plurality of volatile memory banks for caching write data prior to being written to disk drives. Critical data is stored into a first subset of the memory banks, leaving a second subset of memory banks storing only non-critical data. Critical data is data that must be retained during a main power loss to avoid loss of write-cached user data. Critical data includes the write-cached user data itself, as well as metadata describing the write-cached user data. When the controller detects a loss of main power, the controller causes the critical memory banks to receive battery power, but disables battery power to the non-critical memory banks in order to extend the length of time the critical memory banks can continue to receive battery power to reduce the likelihood of user data loss.

Claims

1. A write-caching mass storage controller, comprising:

a plurality of volatile memory banks, each having separate power inputs;

a battery, coupled to provide power to said plurality of volatile memory banks via said separate power inputs during a main power loss;

switches, coupled to said battery and the main power, each having a control input, said switches configured to selectively provide power to said plurality of volatile memory banks from the main power or from said battery in response to said control input;

a processor, coupled to said plurality of volatile memory banks, configured to control storage of critical data to a first subset of said plurality of volatile memory banks and to refrain from controlling storage of said critical data to a second subset of said plurality of volatile memory banks, wherein said first and second subset are mutually exclusive, wherein said critical data comprises data which must be retained during said main power loss to avoid loss of write-cached user data, wherein said processor is configured to execute programs; and

control logic, coupled to said control input of said switches, configured to receive information from said processor specifying which of said plurality of volatile memory banks is included in each of said first and second subsets, and configured to control said switches to;

provide main power to said plurality of volatile memory banks under normal conditions; and

provide battery power to said first subset of volatile memory banks and disable said second subset of said plurality of volatile memory banks from receiving power from said battery in response to detecting said loss of main power.

2. The mass storage controller as recited in claim 1, wherein said critical data comprises said write-cached user data.

3. The mass storage controller as recited in claim 2, wherein said critical data further comprises metadata, said metadata describing said write-cached user data.

4. The mass storage controller as recited in claim 3, wherein said metadata specifies locations of said write-cached user data in said first subset of said plurality of volatile memory banks.

5. The mass storage controller as recited in claim 3, wherein said metadata specifies locations on one or more storage devices controlled by the controller to which said write-cached user data is to be written.

6. The mass storage controller as recited in claim 5, wherein said one or more storage devices comprise disk drives.

7. The mass storage controller as recited in claim 3, wherein said metadata comprises parity logs, used by said processor to fix RAID level 5 write holes.

8. The mass storage controller as recited in claim 3, wherein said metadata comprises debug logs.

9. The mass storage controller as recited in claim 1, wherein said control logic is further configured to place said first subset of said plurality of volatile memory banks into a low power mode in response to detecting said main power loss.

10. The mass storage controller as recited in claim 9, wherein said low power mode comprises a dynamic random access memory (DRAM) self-refresh mode.

11. The mass storage controller as recited in claim 1, wherein said plurality of volatile memory banks comprise banks of dynamic random access memory (DRAM).

12. The mass storage controller as recited in claim 1, wherein said plurality of volatile memory banks occupy separate address ranges within an address space of said processor.

13. The mass storage controller as recited in claim 1, wherein said plurality of volatile memory banks comprise physically separate memory devices, said memory devices having said separate power inputs.

14. The mass storage controller as recited in claim 13, wherein said physically separate memory devices comprise separate integrated circuits.

15. The mass storage controller as recited in claim 1, wherein the mass storage controller is a redundant array of inexpensive disks (RAID) controller and said processor performs RAID functions.

16. The mass storage controller as recited in claim 1, wherein said control logic comprises said processor.

17. The mass storage controller as recited in claim 1, wherein said first and second subsets of said plurality of volatile memory banks are determined by a memory map of program data provided to a compiler/linker that compiles and links software executed by said processor.

18. A method for reducing battery power consumption during a main power supply loss to reduce the likelihood of loss of user write-cached data in a write-caching mass storage controller, comprising:

supplying power from the main power supply to first and second subsets of a plurality of volatile memory banks of the controller, wherein the first and second subset are mutually exclusive;

receiving information from a processor indicating that the first subset of the plurality of volatile memory banks is storing critical data and that the second subset of the plurality of volatile memory banks is not storing critical data, wherein the critical data comprises data which must be retained during the main power supply loss to avoid loss of write-cached user data;

storing critical data to the first subset of the plurality of volatile memory banks in exclusion of the second subset of the plurality of volatile memory banks, while said supplying power from the main power supply to the first and second subsets of the plurality of volatile memory banks of the controller;

detecting the main power supply loss, after said storing the critical data;

supplying power from the battery to the first subset of the plurality of volatile memory banks in response to said detecting the main power supply loss; and

disabling the second subset of the plurality of volatile memory banks from receiving power from the battery in response to said detecting the main power supply loss.

19. The method as recited in claim 18, wherein the critical data comprises the write-cached user data.

20. The method as recited in claim 19, wherein the critical data further comprises metadata, the metadata describing the write-cached user data.

21. The method as recited in claim 20, wherein the metadata specifies locations of the write-cached user data in the first subset of the plurality of volatile memory banks.

22. The method as recited in claim 20, wherein the metadata specifies locations on one or more storage devices controlled by the controller to which the write-cached user data is to be written.

23. The method as recited in claim 22, wherein the one or more storage devices comprise disk drives.

24. The method as recited in claim 20, wherein the metadata comprises parity logs, used to fix RAID level 5 write holes.

25. The method as recited in claim 20, wherein the metadata comprises debug logs.

26. The method as recited in claim 18, further comprising:

placing the first subset of the plurality of volatile memory banks into a low power mode in response to said detecting the main power loss.

27. The method as recited in claim 26, wherein the low power mode comprises a dynamic random access memory (DRAM) self-refresh mode.

28. The method as recited in claim 18, wherein the plurality of volatile memory banks comprise banks of dynamic random access memory (DRAM).

29. The method as recited in claim 18, wherein the plurality of volatile memory banks occupy separate address ranges within an address space of a processor of the controller.

30. The method as recited in claim 26, further comprising:

assigning locations of the critical data within the address ranges of the first subset of the plurality of volatile memory banks, prior to said storing information indicating the first and second subsets.

31. The method as recited in claim 18, wherein the plurality of volatile memory banks comprise physically separate memory devices, the memory devices having the separate power inputs.

32. The method as recited in claim 31, wherein the physically separate memory devices comprise separate integrated circuits.

33. The method as recited in claim 18, wherein the mass storage controller is a redundant array of inexpensive disks (RAID) controller.

34. The method as recited in claim 18, further comprising:

determining said first and second subsets of said plurality of volatile memory banks by a memory map of program data provided to a compiler/linker that compiles and links software executed by said processor, prior to said supplying power from the main power supply.

43. The mass storage controller as recited in claim 33, wherein said first and second subsets of said plurality of volatile memory banks are determined by a memory map of program data provided to a compiler/linker that compiles and links software executed by said processor.

35. A write-caching mass storage controller, comprising:

a plurality of volatile memory banks, each having separate power inputs;

a battery, coupled to provide power to said plurality of volatile memory banks via said separate power inputs, during a main power loss; and

switches, coupled to said battery and the main power, each having a control input, said switches configured to selectively provide power to said plurality of volatile memory banks from the main power or from said battery in response to said control input;

a processor, coupled to said plurality of volatile memory banks and to said control input of said switches, configured to control storage of critical data to a first subset of said plurality of volatile memory banks and to refrain from controlling storage of said critical data to a second subset of said plurality of volatile memory banks, wherein said first and second subset are mutually exclusive, wherein said critical data comprises data which must be retained during said main power loss to avoid loss of write-cached user data, wherein said processor is configured to execute programs, said processor further configured to control said switches to;

provide main power to said plurality of volatile memory banks under normal conditions; and

provide battery power to said first subset of volatile memory banks and, disable said second subset of said plurality of volatile memory banks from receiving power from said battery in response to detecting the loss of main power.

36. The mass storage controller as recited in claim 35, wherein said critical data comprises said write-cached user data.

37. The mass storage controller as recited in claim 36, wherein said critical data further comprises metadata, said metadata describing said write-cached user data.

38. The mass storage controller as recited in claim 37, wherein said metadata specifies locations of said write-cached user data in said first subset of said plurality of volatile memory banks.

39. The mass storage controller as recited in claim 37, wherein said metadata specifies locations on one or more storage devices controlled by the controller to which said write-cached user data is to be written.

40. The mass storage controller as recited in claim 37, wherein said metadata comprises parity logs, used by said processor to fix RAID level 5 write holes.

41. The mass storage controller as recited in claim 35, wherein said control logic is further configured to place said first subset of said plurality of volatile memory banks into a low power mode in response to detecting said main power loss.

42. The mass storage controller as recited in claim 35, wherein said plurality of volatile memory banks occupy separate address ranges within an address space of said processor.