Apparatus and method for PFM buck-or-boost converter with smooth transition between modes

• US 7,495,419 B1
• Filed: 04/03/2006
• Issued: 02/24/2009
• Est. Priority Date: 04/03/2006
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Ju, Shu-Ing
• Primary Examiner(s): Ullah; Akm E
• Assistant Examiner(s): BEHM, HARRY RAYMOND
• Application Number:
  US11/397,425
• Time in Patent Office: 1,058 Days
• Field of Search: 323/259, 323/225, 323/284, 323222-224, 323/285
• US Class Current: 323/259
• CPC Class Codes: G05F 1/62 using bucking or boosting dc sources
• CPC Class Codes: H02M 3/1582 Buck-boost converters H02M3/1584 takes precedence
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

A PFM buck-or-boost converter is provided. The converter includes, inter alia, a hysteretic comparator, current sense circuitry, a logic circuit, drivers, current sense circuitry, a first buck switch, and a first boost switch. The current sense circuitry asserts signal Z if the current through the boost switch (from the load to the inductor) is greater than zero, and unasserts Z otherwise. Additionally, the current sense circuitry asserts signal I if the current through the buck switch is greater than a fixed current limit value, and unasserts I otherwise. The logic circuit employs the hysteretic comparator output, signal Z, and signal I to control the switches, and to determine whether to operate in buck regulation mode or boost regulation mode.

Claims

1. A circuit for DC-DC conversion, comprising:

a pulse-frequency modulation buck-or-boost regulator controller that is operable to control regulation of an output voltage, wherein the pulse-frequency modulation buck-or-boost regulator includes;

a first comparator that is arranged to compare a feedback signal to a reference voltage, wherein the feedback signal is based, at least in part, on the output voltage;

a control logic circuit having at least a first input, a second input, a third input, a first output, and a second output, wherein;

the first input of the control logic circuit is coupled to the first comparator;

the control logic circuit is configured to control a first buck switch by providing a first switch control signal at the first output of the control logic circuit such that the first switch control signal causes the first buck switch to remain on throughout boost mode;

the control logic circuit is configured to control a first boost switch by providing a second switch control signal at the second output of the control logic circuit such that the first switch control signal causes the first boost switch to remain on throughout buck mode; and

wherein the control logic circuit is configured to determine whether to operate according to buck mode or boost mode, wherein the determination of whether to change from buck mode to boost mode is based, at least in part, on whether a current through the first boost switch is greater than zero for a first pre-determined period of time.

2. The circuit of claim 1, wherein the control logic circuit is configured to determine whether to operate according to buck mode or boost mode further based, at least in part, on whether a current through the first buck switch is less than a pre-determined value for a second pre-determined period of time.

3. The circuit of claim 1, wherein the control logic circuit is configured such that the determination of whether to change from boost mode to buck mode is based, at least in part, on whether a current through the first boost switch is less than zero for approximately the first pre-determined period of time.

4. The circuit of claim 1, wherein the control logic circuit is configured such that the determination of whether to change from boost mode to buck mode is based, at least in part, on whether a current through the first buck switch is greater than a pre-determined value for a second pre-determined period of time.

5. The circuit of claim 4, wherein the control logic circuit is configured such that the determination of whether to change from boost mode to buck mode is further based, at least in part, on whether a current through the first boost switch is less than zero for approximately the first pre-determined period of time.

6. The circuit of claim 1, further comprising:

a second comparator that is arranged to compare a second feedback voltage to a second reference voltage, and to provide a second comparator output signal based on the comparison, wherein the second feedback signal is based, at least in part, on an input voltage at an input node, wherein the first comparator is a hysteretic comparator, the first comparator is operable to provide a first comparator output signal based on the comparison of the feedback signal with the reference voltage, and wherein the control logic circuit is arranged to receive the first and second comparator output signals.

7. The circuit of claim 6, wherein

the control logic block is configured to, as long as the first comparator output signal remains asserted, cause a change from buck mode to boost mode only if one of the following two conditions occurs:

the current through the first boost switch, passing from a load to an inductor, is greater than zero for a pre-determined period of time; and

the current through the first buck switch, passing from an input node to the inductor, is less than the pre-determined value for the second pre-determined period of time; and

wherein the control logic block is configured to, as long as the first comparator output signal remains asserted, determine a change from boost mode to buck mode only if one of the following two conditions occurs;

the current through the first boost switch, passing from a load to an inductor, is less than zero for a first pre-determined period of time; and

the current through the first buck switch, passing from an input node to the inductor, is greater than the pre-determined value for the second pre-determined period of time.

8. The circuit of claim 6, wherein

the control logic block is configured to determine a change from buck mode to boost mode only if one of the following three conditions occurs:

the current through the first boost switch, passing from a load to an inductor, is greater than zero for a pre-determined period of time while the first comparator output signal is asserted;

the current through the first buck switch, passing from an input node to the inductor, is less than the pre-determined value for the second pre-determined period of time while the first comparator output signal is asserted; and

a rising edge occurs in the first comparator output signal and the second comparator output signal is unasserted; and

wherein the control logic block is configured to determine a change from boost mode to buck mode if and only if one of the following three conditions occurs;

the current through the first boost switch, passing from a load to an inductor, is less than zero for a first pre-determined period of time while the first comparator output signal is asserted;

the current through the first buck switch, passing from an input node to the inductor, is greater than the pre-determined value for the second pre-determined period of time while the first comparator output signal is asserted; and

a rising edge occurs in the first comparator output signal and the second comparator output signal is asserted.

9. A circuit for DC-DC conversion, comprising:

a first buck switch that is coupled between an input voltage node and a first switch node;

a second buck switch that is coupled to the first switch node;

a first boost switch that is coupled between a second switch node and an output voltage node;

a second boost switch that is coupled to the second switch node;

a pulse-frequency modulation buck-or-boost regulator controller, including;

a first comparator having a first input that is coupled to a first feedback node, a second input that is coupled to a first reference node, and an output;

a control logic circuit that includes at least a first input that is coupled to the output of the first comparator, wherein;

the control logic circuit is configured to, during a buck regulation mode, cause the first boost switch to remain on and the second buck switch to remain off;

the control logic circuit is configured to, during a boost regulation mode, cause the first buck switch to remain on and the second buck switch to remain off; and

wherein the control logic circuit is configured to determine whether to change regulation from buck mode to boost mode based, at least in part, on whether a current through the first buck switch is less than a pre-determined value for a pre-determined period of time.

10. The circuit of claim 9, wherein

the pulse-frequency modulation buck-or-boost regulator controller further includes a second comparator having a first input that is coupled to the second switch node, a second input that is coupled to a second reference voltage node, and an output that is coupled to the second input of the control logic circuit.

11. The circuit of claim 9, wherein

the pulse frequency modulation buck-or-boost regulator controller further includes a second comparator having a first input that is coupled to a second feedback node, a second input that is coupled to a second reference node, and an output, wherein the first comparator is arranged to receive a first feedback signal at the first feedback node;

the first feedback signal is based, at least in part, on the output voltage;

the second comparator is arranged to receive a second feedback signal at the second feedback node; and

wherein the second feedback signal is based, at least in part, on the input voltage.

12. The circuit of claim 9, wherein

the pulse-frequency modulation buck-or-boost regulator controller further includes a second comparator having a first input that is coupled to the first switch node, a second input that is coupled to a second reference voltage node, and an output that is coupled to the second input of the control logic circuit.

13. The circuit of claim 12, wherein

the pulse-frequency modulation buck-or-boost regulator controller further includes a third comparator having a first input that is coupled to the second switch node, a second input that is coupled to a third reference voltage node, and an output that is coupled to the third input of the control logic circuit.

14. The circuit of claim 13, wherein

the pulse frequency modulation buck-or-boost regulator controller further includes a fourth comparator having a first input that is coupled to a second feedback node, a second input that is coupled to a fourth reference node, and an output, wherein the first comparator is arranged to receive a first feedback signal at the first feedback node, wherein the first feedback signal is based, at least in part, on the output voltage;

and wherein the fourth comparator is arranged to receive a second feedback signal at the second feedback node, wherein the second feedback signal is based, at least in part, on the input voltage.

15. A method for DC-DC conversion, comprising:

at power-on, making an initial determining as to whether to operate in buck mode or boost mode;

during boost mode, performing boost regulation to provide an output voltage, wherein performing boost regulation includes;

opening and closing a first boost switch based on pulse frequency modulation; and

keeping a first buck switch closed during boost mode;

during buck mode, performing buck regulation to provide an output voltage, wherein performing buck regulation includes;

opening and closing a first buck switch based on pulse frequency modulation; and

keeping a first boost switch closed during buck mode;

during buck mode, determining whether to change from buck mode to boost mode; and

during boost mode, determining whether to change from boost mode to buck mode, wherein the determination of whether to change from buck mode to boost mode is based, at least in part, on whether a current through the first boost switch is greater than zero for a pre-determined period of time.

16. A method for DC-DC conversion, comprising:

at power-on, making an initial determining as to whether to operate in buck mode or boost mode;

during boost mode, performing boost regulation to provide an output voltage, wherein performing boost regulation includes;

opening and closing a first boost switch based on pulse frequency modulation; and

keeping a first buck switch closed during boost mode;

during buck mode, performing buck regulation to provide an output voltage, wherein performing buck regulation includes;

opening and closing a first buck switch based on pulse frequency modulation; and

keeping a first boost switch closed during buck mode;

during buck mode, determining whether to change from buck mode to boost mode; and

during boost mode, determining whether to change from boost mode to buck mode, wherein the determination of whether to change from buck mode to boost mode is based, at least in part, on whether a current through the first buck switch is less than the pre-determined value for a pre-determined period of time.

17. A method for DC-DC conversion, comprising:

at power-on, making an initial determining as to whether to operate in buck mode or boost

during boost mode, performing boost regulation to provide an output voltage, wherein performing boost regulation includes;

opening and closing a first boost switch based on pulse frequency modulation; and

keeping a first buck switch closed during boost mode;

during buck mode, performing buck regulation to provide an output voltage, wherein performing buck regulation includes;

opening and closing a first buck switch based on pulse frequency modulation; and

keeping a first boost switch closed during buck mode;

during buck mode, determining whether to change from buck mode to boost mode; and

during boost mode, determining whether to change from boost mode to buck mode, wherein the determination of whether to change from boost mode to buck mode is based, at least in part, on whether a current through the first boost switch is less than zero for approximately the first pre-determined period of time.

18. The method of claim 17, wherein the determination of whether to change from boost mode to buck mode is further based, at least in part, on whether a current through the first buck switch is greater than a pre-determined value for a pre-determined period of time.

19. The method of claim 17, further comprising:

employing a first voltage divider to provide a first feedback voltage from the output voltage;

employing a hysteretic comparator to provide a first comparator output signal based on a comparison of the first feedback voltage with a first reference voltage;

employing a second voltage divider to provide a second feedback voltage from an input voltage; and

employing another comparator to provide a second comparator output signal based on a comparison of the second feedback voltage with the first reference voltage.

20. The method of claim 19, wherein

changing from buck mode to boost mode occurs only if one of the following three conditions occurs:

the current through the first boost switch, passing from a load to an inductor, is greater than zero for a pre-determined period of time while the first comparator output signal is asserted;

the current through the first buck switch, passing from an input node to the inductor, is less than the pre-determined value for the second pre-determined period of time while the first comparator output signal is asserted; and

a rising edge occurs in the first comparator output signal and the second feedback signal is greater than the second reference voltage; and

wherein changing from boost mode to buck mode occurs if and only if one of the following three conditions occurs;

the current through the first boost switch, passing from a load to an inductor, is less than zero for a first pre-determined period of time while the first comparator output signal is asserted;

the current through the first buck switch, passing from an input node to the inductor, is greater than the pre-determined value for the second pre-determined period of time while the first comparator output signal is asserted; and

a rising edge occurs in the first comparator output signal and the second feedback signal is less than the second reference voltage.

21. A circuit for DC-DC conversion, comprising:

a first buck switch that is coupled between an input voltage node and a first switch node;

a second buck switch that is coupled to the first switch node;

a first boost switch that is coupled between a second switch node and an output voltage node;

a second boost switch that is coupled to the second switch node;

a pulse-frequency modulation buck-or-boost regulator controller that is arranged to control regulation of the output voltage so that the output voltage is regulated to a value that is based on a reference voltage, wherein the pulse-frequency modulation buck-or-boost regulator controller includes;

a first comparator having a first input that is coupled to a first feedback node, a second input that is coupled to a first reference node, and an output;

a control logic circuit that includes at least a first input that is coupled to the output of the first comparator, wherein;

the control logic circuit is configured to, during a buck regulation mode, cause the first boost switch to remain on and the second buck switch to remain off;

the control logic circuit is configured to, during a boost regulation mode, cause the first buck switch to remain on and the second buck switch to remain off, and

wherein the control logic circuit is configured to determine whether to change regulation from boost mode to buck mode based, at least in part, on whether a current through the first buck switch is greater than a pre-determined value for a pre-determined period of time, wherein the pulse-frequency modulation buck-or-boost regulator controller continues to regulate the output voltage to a value that is based on the reference voltage when the regulation changes from boost mode to buck mode based, at least in part, on whether a current through the first buck switch is greater than a pre-determined value for a pre-determined period of time.