Output circuit for semiconductor device, semiconductor device having output circuit, and method of adjusting characteristics of output circuit

• US 7,495,453 B2
• Filed: 04/12/2007
• Issued: 02/24/2009
• Est. Priority Date: 01/19/2005
• Status: Active Grant

• Current Assignee: Longitude Licensing Limited (Vector Capital Corporation)
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: Fujisawa, Hiroki
• Primary Examiner(s): Dole; Timothy J
• Assistant Examiner(s): He; Amy
• Application Number:
  US11/783,787
• Publication Number:
  US 20070194798A1
• Time in Patent Office: 684 Days
• Field of Search: 324/601, 324/765, 326/30
• US Class Current: 324/601
• CPC Class Codes: G01R 31/31713 Input or output interfaces for test, e.g. test pins, buffers for scan test G01R31/318572
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: H03H 11/28 Impedance matching networks
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance

Abstract

To decrease the circuit scale necessary for the calibration of the output circuit and to decrease the time required for the calibration operation. The invention includes a first output buffer and a second output buffer that are connected to a data pin, and a calibration circuit that is connected to a calibration pin. The first output buffer and the second output buffer include plural unit buffers. The unit buffers have mutually the same circuit structures. With this arrangement, the impedances of the first output buffer and the second output buffer can be set in common, based on the calibration operation using the calibration circuit. Consequently, both the circuit scale necessary for the calibration operation and the time required for the calibration operation can be decreased.

Claims

1. An output circuit for a semiconductor device, comprising:

a plurality of impedance-adjustable unit buffers connected in common to a data pin, the plurality of unit buffers being divided into at least first and second groups, each unit buffer including a plurality of parallel-connected transistors each individually on/off controlled;

a first pre-stage circuit that activates one or more unit buffers belonging to the first group;

a second pre-stage circuit that activates one or more unit buffers belonging to the second group; and

an output control circuit that independently selects the first and second pre-stage circuits.

2. The output circuit for a semiconductor device as claimed in claim 1, wherein the unit buffers have mutually substantially the same circuit structures.

3. The output circuit for a semiconductor device as claimed in claim 2, further comprising a calibration circuit that controls impedances of the plurality of unit buffers in common.

4. The output circuit for a semiconductor device as claimed in claim 3, wherein said calibration circuit includes a replica buffer having substantially the same circuit structure as that of the unit buffer.

5. The output circuit for a semiconductor device as claimed in claim 3 wherein said calibration circuit sets the plurality of unit buffers to the same impedance as each other.

6. The output circuit for a semiconductor device as claimed in claim 1 wherein a number of unit buffers belonging to the first group is different from a number of unit buffers belonging to the second group.

7. The output circuit for a semiconductor device as claimed in claim 1 wherein the output control circuit selects at least the first pre-stage circuit at a data output time, and the output control circuit selects at least the second pre-stage circuit at an ODT operation time.

8. The output circuit for a semiconductor device as claimed in claim 7, wherein the output control circuit also selects the second pre-stage circuit at the data output time.

9. The output circuit for a semiconductor device as claimed in claim 8, wherein the output control circuit does not select the first pre-stage circuit at the ODT operation time.

10. The output circuit for a semiconductor device as claimed in claim 7, wherein the output control circuit does not select the first pre-stage circuit at the ODT operation time.

11. The output circuit for a semiconductor device as claimed in claim 1 wherein each of said unit buffers includes a pull-up circuit and a pull-down circuit.

12. The output circuit for a semiconductor device as claimed in claim 1 wherein each of said unit buffers includes parallel-connected P-channel MOS transistors and parallel-connected N-channel MOS transistors.

13. The output circuit for a semiconductor device as claimed in claim 12 wherein said P-channel MOS transistors include at least two P-channel MOS transistors having different gate width to gate length ratio from each other, and said N-channel MOS transistors include at least two N-channel MOS transistors having different gate width to gate length ratio from each other.

14. The output circuit for a semiconductor as claimed in claim 1, wherein each unit buffer includes a pull-up circuit including a plurality of transistors and a pull-down circuit including a plurality of transistors.

15. An output circuit for a semiconductor device, comprising:

a first output buffer having parallel-connected two or more impedance-adjustable unit buffers connected in common to a data pin; and

a second output buffer having one or parallel-connected two or more impedance-adjustable unit buffers connected in common to the data pin, wherein

the unit buffers have mutually substantially the same circuit structures,

each unit buffer included in the first and second output buffers includes a plurality of parallel-connected transistors each individually on/off controlled, and

a number of unit buffers included in the first output buffer is different from that of the second output buffer.

16. The output circuit for a semiconductor device as claimed in claim 15, wherein the first output buffer is activated at least at a data output time and the second output buffer is activated at least at an ODT operation time.

17. The output circuit for a semiconductor device as claimed in claim 16, wherein said second output buffer is also activated at the data output time.

18. The output circuit for a semiconductor device as claimed in claim 17 wherein said first output buffer is inactivated at least at the ODT operation time.

19. The output circuit for a semiconductor device claimed in claim 16, wherein said first output buffer is inactivated at least at the ODT operation time.

20. The output circuit for a semiconductor device as claimed in claim 15 further comprising a calibration circuit that controls impedances of the plurality of unit buffers in common.

21. The output circuit for a semiconductor device as claimed in claim 20, wherein said calibration circuit includes a replica buffer having substantially the same circuit structure as that of the unit buffer.

22. The output circuit for a semiconductor device as claimed in claim 20, wherein said calibration circuit sets the plurality of unit buffers to the same impedance as each other.

23. The output circuit for a semiconductor device as claimed in claim 15, wherein each of said unit buffers includes a pull-up circuit and a pull-down circuit.

24. The output circuit for a semiconductor device as claimed in claim 15, wherein each of said unit buffers includes parallel-connected P-channel MOS transistors and parallel-connected N-channel MOS transistors.

25. The output circuit for a semiconductor device as claimed in claim 24, wherein said P-channel MOS transistors include at least two P-channel MOS transistors having different gate width to gate length ratio from each other, and said N-channel MOS transistors include at least two N-channel MOS transistors having different gate width to gate length ratio from each other.

26. The output circuit for a semiconductor as claimed in claim 15 wherein each unit buffer includes a pull-up circuit including a plurality of transistors and a pull-down circuit including a plurality of transistors.

27. An output circuit for a semiconductor device that can perform ODT operation, comprising:

a plurality of impedance-adjustable unit buffers connected in common to a data pin, each unit buffer including a plurality of parallel-connected transistors each individually on/off controlled; and

an output control circuit that activates a first number of unit buffers in common when an ODT impedance is set to a first value and activates a second number of unit buffers in common when the ODT impedance is set to a second value.

28. The output circuit for a semiconductor device as claimed in claim 27, wherein at least parts of the plurality of unit buffers are activated at a data output time.

29. The output circuit for a semiconductor device as claimed in claim 27 further comprising a calibration circuit that controls impedances of the plurality of unit buffers in common.

30. The output circuit for a semiconductor device as claimed in claim 29 wherein said calibration circuit includes a replica buffer having substantially the same circuit structure as that of the unit buffer.

31. The output circuit for a semiconductor device as claimed in claim 29 wherein said calibration circuit sets the plurality of unit buffers to the same impedance as each other.

32. The output circuit for a semiconductor device as claimed in claim 27 wherein each of said unit buffers includes a pull-up circuit and a pull-down circuit.

33. The output circuit for a semiconductor device as claimed in claim 27, wherein each of said unit buffers includes parallel-connected P-channel MOS transistors and parallel-connected N-channel MOS transistors.

34. The output circuit for a semiconductor device as claimed in claim 33 wherein said P-channel MOS transistors include at least two P-channel MOS transistors having different gate width to gate length ratio from each other, and said N-channel MOS transistors include at least two N-channel MOS transistors having different gate width to gate length ratio from each other.

35. The output circuit for a semiconductor as claimed in claim 27 wherein each unit buffer includes a pull-up circuit including a plurality of transistors and a pull-down circuit including a plurality of transistors.