Memory chip architecture with high speed operation

• US 7,495,991 B2
• Filed: 12/04/2007
• Issued: 02/24/2009
• Est. Priority Date: 03/31/2005
• Status: Active Grant

• Current Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Original Assignee: Hynix Semiconductor Incorporated (SK Hynix Inc.)
• Inventors: Lee, Geun-Il, Joo, Yong-Suk
• Primary Examiner(s): Nguyen; Viet Q
• Application Number:
  US11/999,465
• Publication Number:
  US 20080089107A1
• Time in Patent Office: 448 Days
• Field of Search: 365/230.01, 365/230.03, 365/63, 365/189.03, 365/189.18, 365/189.08
• US Class Current: 365/230.03
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines

Abstract

A semiconductor memory device includes at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device; a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device; a global line block, arranged in a center of the semiconductor memory device, for transmitting inputted command and address; and at least one bank area, arranged between the global line block and the data transmission block, each bank area containing plural data I/O blocks located in a side of the data transmission block and plural control blocks located in a side of the global line block.

Claims

1. A semiconductor memory device comprising:

at least one data transmission block including data I/O pads arranged in a major-axis side of the semiconductor memory device;

a command and address transmission block including address and command input pads arranged in at least one minor-axis side of the semiconductor memory device;

a global line block, arranged in a center of the semiconductor memory device, for transmitting inputted command and address;

at least one bank area, arranged between the global line block and the data transmission block, each bank area containing a plurality of banks, a plurality of data I/O blocks located closer to the data transmission block than the global line blocks—

and a plurality of control blocks located closer to the global line block than the data transmission block; and

decoding control blocks corresponding to the plurality of banks, respectively,

wherein the inputted command and address are transmitted to the decoding control blocks via the center of the semiconductor memory device.

2. The semiconductor memory device as recited in claim 1, wherein the data I/O block includes an I/O sense amplifier and a write driver.

3. The semiconductor memory device as recited in claim 2, wherein the control block includes a column decoder.

4. The semiconductor memory device as recited in claim 3, wherein the data I/O block and the control block included in the bank area corresponds to each of the plurality of banks included in the bank area.

5. The semiconductor memory device as recited in claim 4, wherein the bank area further includes a plurality of row decoders, arranged between and corresponding to the plurality of banks, respectively.

6. The semiconductor memory device as recited in claim 5, wherein the semiconductor memory device includes two bank areas, each having four banks.

7. The semiconductor memory device as recited in claim 6, wherein the semiconductor memory device includes two data transmission blocks, each data transmission block including a half of data I/O pads corresponding to a data bandwidth of the semiconductor memory device.

8. The semiconductor memory device as recited in claim 5, wherein the decoding control block controls the column decoder and the row decoder of a bank based on the inputted command and address via the command and address transmission block.

9. The semiconductor memory device as recited in claim 8, wherein the decoding control block is arranged in the global line block.

10. The semiconductor memory device as recited in claim 1, further comprising:

a first transmitter for transmitting internal addresses and commands based on the inputted address and command from the command and address transmission block to a center of the global line block; and

a second transmitter for delivering the internal addresses and commands transmitted to the global line block to the decoding control blocks.