Power-efficient technique for invoking a co-processor

• US 7,496,770 B2
• Filed: 09/30/2005
• Issued: 02/24/2009
• Est. Priority Date: 09/30/2005
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Gupta, Vikram
• Primary Examiner(s): Suryawanshi; Suresh K
• Application Number:
  US11/241,032
• Publication Number:
  US 20070079161A1
• Time in Patent Office: 1,243 Days
• Field of Search: 713/300, 713/323, 713/320
• US Class Current: 713/300
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Various embodiments are disclosed relating to power-efficient techniques for invoking a co-processor. In an example embodiment, a computer system may include a first processor (e.g., a host processor) and a second processor (e.g., a co-processor). The first processor may instruct the second processor to perform an operation repeatedly on a data stream. The first processor may be placed in a low power state. The second processor may perform the operation repeatedly on the data stream while the first processor remains in the low-power state.

Claims

1. A method of processing data in a computer system having a first processor and a second processor, the method comprising:

sending an instruction to the second processor to perform an operation on a data stream, wherein the instruction includes a command field and an execution mode field, a value of the execution mode field specifying one of a plurality of modes of execution including a regular mode indicating the instruction should be executed by the second processor once before awaking the first processor from a low power sleep mode, and a repeat mode indicating that the instruction should be executed repeatedly without further instructions from the first processor;

placing the first processor in a low power state; and

performing the operation on the data stream with the second processor once or repeated based on the value of the execution mode field while the first processor remains in the low-power sleep mode.

2. The method of claim 1, further comprising:

receiving an error signal generated by the second processor; and

waking up the first processor in response to the error signal.

3. The method of claim 2, wherein the error signal is generated in response to inactivity by the second processor for a time period greater than a predetermined time period.

4. The method of claim 1, further comprising waking up the first processor after a predetermined time period has elapsed after the first processor has entered the low-power sleep mode.

5. The method of claim 1, wherein said instructing comprises instructing the second processor to perform the operation repeatedly on the data stream for a predetermined number of times and, after the operation has been performed for the predetermined number of times, to send a signal to the first processor to wake up the first processor.

6. The method of claim 1, further comprising receiving the data stream from a wireless communications link.

7. The method of claim 1, further comprising receiving a signal from a peripheral device at the second processor to wake up the second processor from a low power state, wherein the signal is received while the first processor is in the low power state.

8. The method of claim 1, further comprising configuring a direct memory access channel for communication between the second processor and a memory.

9. The method of claim 1, further comprising:

determining a data type of the data stream; and

selecting the operation for the second processor to perform on the data stream based on the data type.

10. A method comprising:

receiving an instruction at a second processor from a first processor, the instruction including a command field and an execution mode field, a value of the execution mode field specifying one of a plurality of modes of execution including a regular mode indicating the instruction should be executed by the second processor once before awaking the first processor from a low power sleep mode, and a repeat mode indicating that the instruction should be executed repeatedly without further instructions from the first processor; and

executing the instruction by the second processor once or repeated based on the value of the execution mode field.

11. A computer system comprising:

a memory;

a first processor; and

a second processor,

wherein the first processor is configured to send an instruction to the second processor to perform an operation on a data stream, wherein the instruction includes a command field and an execution mode field, a value of the execution mode field specifying one of a plurality of modes of execution including a regular mode indicating the instruction should be executed by the second processor once before awaking the first processor from a low power sleep mode, and a repeat mode indicating that the instruction should be executed repeatedly without further instructions from the first processor,

and wherein the first processor is configured to enter a low power state after instructing the second processor to perform repeatedly the operation,

and wherein the second processor is configured to, based on the value of the execution mode field, perform the operation on the data stream once or repeatedly while the first processor remains in the low-power sleep mode.

12. The computer system of claim 11 wherein the first processor comprises a host processor and the second processor comprises a co-processor.

13. The computer system of claim 11, further comprising a direct memory access device coupled to the second processor.

14. The computer system of claim 11, wherein the first processor is a central processing unit and the second processor is a co-processor.

15. The computer system of claim 11, further comprising a memory device adapted and configured to store instructions for instructing the first processor to send the instruction to the second processor.

16. The computer system of claim 11, wherein the second processor is adapted to send a signal to the first processor to wake up the first processor.

17. The computer system of claim 16, wherein the second processor is adapted to send the signal to the first processor after the second processor has performed the operation a predetermined number of times.

18. The computer system of claim 16 wherein the second processor is adapted to send the signal to the first processor when performance of the operation by the second processor generates an error.

19. The computer system of claim 16, wherein

the second processor is adapted to enter a low power state upon no activity while the first processor is in a low power state;

and

wherein, while the first processor remains in a low power state, the second processor is adapted to awaken from its low power state upon receipt of a wake up signal from a peripheral device.