Identifying code for compilation
First Claim
Patent Images
1. A processor, comprising:
- fetch logic adapted to fetch a set of instructions from memory, the set comprising a subset of instructions;
decode logic coupled to the fetch logic and adapted to process the set of instructions, wherein the decode logic comprises a vector table comprising an entry for each instruction in an instruction set of the processor, each entry in the vector table comprising a first bit that indicates whether or not a micro-sequence corresponding to the instruction is to be executed when the instruction is decoded, and a second bit that indicates whether or not the instruction is to be executed if the micro-sequence is executed; and
a clock coupled to the decode logic;
wherein when the decode logic processes an instruction from the set of instructions and when the first bit in the entry for the instruction indicates the micro-sequence is to be executed, the micro-sequence corresponding to the instruction is executed to enable a counter external to the processor, wherein enabling the counter causes the clock to increment the counter while the subset is processed,wherein a status of the counter is manipulated to determine an efficiency level pertaining to the subset of instructions.
1 Assignment
0 Petitions
Accused Products
Abstract
A processor comprising fetch logic adapted to fetch a set of instructions from memory, the set comprising a subset of instructions. The processor further comprises decode logic coupled to the fetch logic and adapted to process the set of instructions, and a clock coupled to the decode logic. When processed, an instruction from the set causes the clock to increment a counter external to the processor while the subset is processed. A status of the counter is manipulated to determine an efficiency level pertaining to the subset of instructions.
15 Citations
30 Claims
-
1. A processor, comprising:
-
fetch logic adapted to fetch a set of instructions from memory, the set comprising a subset of instructions; decode logic coupled to the fetch logic and adapted to process the set of instructions, wherein the decode logic comprises a vector table comprising an entry for each instruction in an instruction set of the processor, each entry in the vector table comprising a first bit that indicates whether or not a micro-sequence corresponding to the instruction is to be executed when the instruction is decoded, and a second bit that indicates whether or not the instruction is to be executed if the micro-sequence is executed; and a clock coupled to the decode logic; wherein when the decode logic processes an instruction from the set of instructions and when the first bit in the entry for the instruction indicates the micro-sequence is to be executed, the micro-sequence corresponding to the instruction is executed to enable a counter external to the processor, wherein enabling the counter causes the clock to increment the counter while the subset is processed, wherein a status of the counter is manipulated to determine an efficiency level pertaining to the subset of instructions. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 29)
-
-
12. An electronic device, comprising:
-
a decode logic adapted to process a set of instructions, wherein the decode logic comprises a vector table comprising an entry for each instruction in an instruction set, each entry in the vector table comprising a first field that indicates whether or not a micro-sequence corresponding to the instruction is to be executed when the instruction is decoded, and a second field that indicates whether or not the instruction is to be executed if the micro-sequence is executed; a clock coupled to the decode logic; and a memory coupled to the decode logic and comprising a counter; wherein the decode logic is further adapted to process an instruction, wherein the micro-sequence corresponding to the instruction is executed to enable the counter when the first field in the entry for the instruction indicates the micro-sequence is to be executed, wherein enabling the counter causes the clock to increment the counter with each clock pulse, the counter incremented only while the set of instructions is processed, wherein a status of the counter is manipulated to determine an efficiency level pertaining to the set of instructions. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 30)
-
-
23. A method, comprising:
-
decoding an instruction, wherein a micro-sequence corresponding to the instruction is executed when a first field in an entry of a decoder vector table corresponding to the instruction indicates that the micro-sequence is to be executed, wherein the micro-sequence enables a counter external to a processor, wherein enabling the counter causes a processor clock to increment the counter while instructions are processed, and wherein when a second field in the entry indicates that the instruction is not be executed, the micro-sequence also performs a function of the instruction, and when the second field indicates that the instruction is to be executed, the instruction is executed after the micro-sequence is executed; processing a first set of instructions, wherein the counter is incremented only while the first set of instructions is processed; after the first set of instructions has been processed, manipulating a status of the counter to determine an efficiency level pertaining to the first set of instructions; and comparing said efficiency level to that of a second set of instructions to determine which of the first set or the second set is to be compiled. - View Dependent Claims (24, 25, 26, 27, 28)
-
Specification